Datasheet

ADC12EU050
SNAS444I –JANUARY 2008–REVISED APRIL 2013 www.ti.com
Bit Description
The SRES is self clearing in approximately 2µs.
0 Software Reset Inactive
1 Software Reset Active
2 SPIOD: SPI Open Drain mode.
0 Digital Logic Output
1 Open Drain Mode. Enables SPI Driver to operate above V
DR
1 SLEEP: Sleep Mode. Powers down the device with the exception of the PLL and the reference blocks. The
time to wake-up from sleep mode is < 10µs.
0 Sleep Mode Inactive
1 Sleep Mode Active
0 PD: Power Down Mode. Completely powers down the device. The power up time is approximately 20ms.
0 PD Mode Inactive, device operates normally
1 PD Mode Active, device powered down
ADC / LVDS Channel Power Down Register
• Address: 02h
• Attributes: Write Only
• Register 03h reads back contents of register 02h
The ADC/LVDS Channel Power Down Register provides the capability to independently power down each ADC
channel.
b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] HEX
Description PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Default 0 0 0 0 0 0 0 0 00 h
Bit Description
7 PD7: Power Down Channel 7
0 Channel Active
1 Channel Power Down
6 PD6: Power Down Channel 6
0 Channel Active
1 Channel Power Down
5 PD5: Power Down Channel
0 Channel Active
1 Channel Power Down
4 PD4: Power Down Channel 4
0 Channel Active
1 Channel Power Down
3 PD3: Power Down Channel 3
0 Channel Active
1 Channel Power Down
2 PD2: Power Down Channel 2
0 Channel Active
1 Channel Power Down
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