Datasheet

ADC
SPI
Controller
(Master)
e.g. DSP,
Microcontroller,
FPGA
serial_in
clock
chip_select_b_1
serial_out
output_enable
V
D
ADC
S
DATA
S
CLK
S
SEL
chip_select_b_N
SDIO Pads
configured in open
drain mode
S
DATA
S
CLK
S
SEL
ADC
S
DATA
S
CLK
S
SEL
SPI
controller
(Master)
e.g. DSP,
Microcontroller,
FPGA
serial_in
clock
chip_select_b
serial_out
output_enable
ADC12EU050
www.ti.com SNAS444I –JANUARY 2008–REVISED APRIL 2013
Programming Guide
THE SERIAL CONTROL INTERFACE
The ADC12EU050 provides several user controlled functions which are accessed through a standard SPI
compatible, 3 wire Serial Interface, as shown in the diagram below.
Figure 25. Three Wire Control Interface
Wired OR mode is supported in order to connect multiple ADC12EU050 devices to one SPI Master. The clock
and data buses are common to all ADC devices, and the chip select S
SEL
is used to control which SPI is
currently active. The SPI master must have a unique pin available for each ADC’s S
SEL
. The diagram below
illustrates the connection.
Figure 26. Multi-Wire Control Interface
When connecting multiple devices, the S
DATA
pin must be set in Open Drain mode. Open Drain mode is enabled
by setting the SPIOD bit in the Top Control Register of all connected ADC12EU050 devices. When S
DATA
is in
open drain mode, the user must ensure that a pull-up resistor is connected to the S
DATA
bus. Further details on
Open Drain mode are given in S
DATA
PAD OPEN DRAIN MODE.
SERIAL CONTROL INTERFACE PROTOCOL
Both read and write transactions are made up of eight address bits and eight data bits. The final address bit of
the address phase determines whether the transaction will be a read transaction or a write transaction – logic
level low for write, logic level high for read. The following diagram shows the protocol.
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