Datasheet

ADC12DC105
(top view)
OF/DCS
V
A
V
A
CLK
V
DR
V
A
V
A
DRGND
PD_A DA7
1
2
3
4
5
6
7
8
9
10
11
12
14
15
13
V
RP
A
PD_B
DB0 (LSB)
V
DR
V
DR
V
REF
DA5 N/C DA8
32
31
45
44
43
42
41
40
39
38
37
35
34
33
36
48 47 46 60 59 58 57 56 55 54 53 51 50 49 52
DRGND
17
18
19 20 21 22 23 24 25 26 27 28 30 16 29
V
IN
A-
V
IN
A+
AGND
AGND
AGND
V
A
AGND
V
IN
B-
DA6
V
CMO
A
V
RN
A
V
CMO
B
V
RN
B
V
RP
B
DRGND
DA4 DA11 (MSB) DA10
* Exposed Pad
V
IN
B+
DB1 DB2 DB3 DB4 DB5
DB8
DB9
DB10
DB11 (MSB)
DRDY
DA0 (LSB)
DA1
DA2
N/C
N/C
DA3
DA9
DB7
DB6
N/C N/C
12-Bit Pipelined
ADC Core
Output
Buffers
Reference
A
Reference
B
Timing
Generation
V
IN
A
2 12
12
DA0-DA11
CHANNEL A
12-Bit Pipelined
ADC Core
Output
Buffers
V
IN
B
2 12
DB0-DB11
CHANNEL B
DRDY
CLK
V
REF
Ref.Decoupling
Ref.Decoupling
3
3
12
ADC12DC105
SNAS469A –SEPTEMBER 2008–REVISED OCTOBER 2008 www.ti.com
Block Diagram
Connection Diagram
Figure 1. WQFN Package
See Package Number NKA0060A
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