Datasheet
1
4
12
AGND
15
AGND
AGND
DR GND
25
DR GND
37
DR GND
51
ADC12DC105
V
A
V
A
V
A
V
A
V
A
V
DR
V
DR
8
16
17
58
60
38
50
3x 0.1 PF
5x 0.1 PF
59
+
10 PF
+3.3V
0.1 PF
20
20
0.1 PF
1
2
V
IN_B
V
IN
A-
V
IN
A+
13
14
50
5
6
0.1 PF
20
20
0.1 PF
1
2
V
IN_A
V
IN
B-
V
IN
B+
2
3
OF/DCS
CLK
Crystal Oscillator
18
19
57
20
PD_A
18 pF
18 pF
9
11
10
AGND
0.1 PF
ADT1-1WT
0.1 PF
V
RP
A
V
RN
A
V
CMO
A
0.1 PF
0.1 PF
1 PF
0.1 PF
0.1 PF
50
7
0.1 PF
0.1 PF
1 PF
0.1 PF
0.1 PF
ADT1-1WT
V
CMO
B
V
RP
B
V
RN
B
V
REF
0.1 PF
V
DR
26
PD_B
+2.5V
OF/DCS
PD_A
PD_B
DA7
DA6
DA5
DA4
(MSB )
DA11
DA10
DA9
DA8
DA3
DA2
DA1
(LSB) DA0
42
43
44
45
46
47
48
49
52
53
54
55
74LCX162244
DRDY
39
DB7
DB6
DB5
DB4
DB10
DB9
DB8
DB3
DB2
DB1
(LSB) DB0
23
24
27
28
29
30
31
32
33
34
35
36
74LCX162244
22:
Channel A
Output Word
Buffered
DRDY
Channel B
Output Word
22:
22:
(MSB )
DA11
ADC12DC105
www.ti.com
SNAS469A –SEPTEMBER 2008–REVISED OCTOBER 2008
DIGITAL OUTPUTS
Digital outputs consist of the CMOS signals DA0-DA11, DB0-DB11, and DRDY.
The ADC12DC105 has 12 CMOS compatible data output pins corresponding to the converted input value for
each channel, and a data ready (DRDY) signal that should be used to capture the output data. Valid data is
present at these outputs while the PD pin is low. Data should be captured and latched with the rising edge of the
DRDY signal.
Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current flows through V
DR
and DRGND. These large charging
current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic
performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will
reduce this problem. The result could be an apparent reduction in dynamic performance.
Figure 22. Application Circuit
POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 0.1 µF capacitor and with a 100 pF ceramic chip capacitor
close to each power pin. Leadless chip capacitors are preferred because they have low series inductance.
As is the case with all high-speed converters, the ADC12DC105 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100 mV
P-P
.
No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be
especially careful of this during power turn on and turn off.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
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