Datasheet
ADC12DC105
SNAS469A –SEPTEMBER 2008–REVISED OCTOBER 2008
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Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may
result in degraded noise performance. Loading any of these pins, other than V
CMO
may result in performance
degradation.
The nominal voltages for the reference bypass pins are as follows:
V
CMO
= 1.5 V
V
RP
= 2.0 V
V
RN
= 1.0 V
OF/DCS Pin
Duty cycle stabilization and output data format are selectable using this quad state function pin. When enabled,
duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to 70% and generate
a stable internal clock, improving the performance of the part. With OF/DCS = V
A
the output data format is 2's
complement and duty cycle stabilization is not used. With OF/DCS = AGND the output data format is offset
binary and duty cycle stabilization is not used. With OF/DCS = (2/3)*V
A
the output data format is 2's complement
and duty cycle stabilization is applied to the clock. If OF/DCS is (1/3)*V
A
the output data format is offset binary
and duty cycle stabilization is applied to the clock. While the sense of this pin may be changed "on the fly," doing
this is not recommended as the output data could be erroneous for a few clock cycles after this change is made.
Note: This signal has no effect when SPI_EN is high and the serial control interface is enabled.
DIGITAL INPUTS
Digital CMOS compatible inputs consist of CLK, PD_A, and PD_B.
Clock Input
The CLK controls the timing of the sampling process. To achieve the optimum noise performance, the clock input
should be driven with a stable, low jitter clock signal in the range indicated in the Electrical Table. The clock input
signal should also have a short transition region. This can be achieved by passing a low-jitter sinusoidal clock
source through a high speed buffer gate. The trace carrying the clock signal should be as short as possible and
should not cross any other signal line, analog or digital, not even at 90°.
The clock signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the
charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade.
This is what limits the minimum sample rate.
The clock line should be terminated at its source in the characteristic impedance of that line. Take care to
maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 for
information on setting characteristic impedance.
It is highly desirable that the the source driving the ADC clock pins only drive that pin. However, if that source is
used to drive other devices, then each driven pin should be AC terminated with a series RC to ground, such that
the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is:
where
• t
PD
is the signal propagation rate down the clock line
• "L" is the line length
• Z
O
is the characteristic impedance of the clock line (12)
This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock
source. Typical t
PD
is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and t
PD
should be
the same (inches or centimeters).
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise
duty cycle is difficult, the ADC12DC105 has a Duty Cycle Stabilizer.
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