Datasheet

ADC
Input
3 pF
V
CMO
0.1 PF
0.1 PF
V
IN
ETC1-1-13
0.1 PF
100:
100:
ETC1-1-13
ADC
Input
18 pF
V
CMO
0.1 PF
0.1 PF
V
IN
ADT1-1WT
50:
0.1 PF
20:
20:
ADC12DC105
www.ti.com SNAS469A –SEPTEMBER 2008–REVISED OCTOBER 2008
Driving the Analog Inputs
The V
IN
+ and the V
IN
− inputs of the ADC12DC105 have an internal sample-and-hold circuit which consists of an
analog switch followed by a switched-capacitor amplifier.
Figure 20 and Figure 21 show examples of single-ended to differential conversion circuits. The circuit in
Figure 20 works well for input frequencies up to approximately 70MHz, while the circuit in Figure 21 works well
above 70MHz.
Figure 20. Low Input Frequency Transformer Drive Circuit
Figure 21. High Input Frequency Transformer Drive Circuit
One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF
transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs
for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the
analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed
to the ADC core.
Input Common Mode Voltage
The input common mode voltage, V
CM
, should be in the range of 1.4V to 1.6V and be a value such that the peak
excursions of the analog signal do not go more negative than ground or more positive than 2.6V. It is
recommended to use V
CMO
(pins 7,9) as the input common mode voltage.
If the ADC12DC105 is operated with V
A
=3.6V, a resistor of approximately 1KΩ should be used from the V
CMO
pin
to AGND. This will help maintain stability over the entire temperature range when using a high supply voltage.
Reference Pins
The ADC12DC105 is designed to operate with an internal or external 1.2V reference. The internal 1.2 Volt
reference is the default condition when no external reference input is applied to the V
REF
pin. If a voltage is
applied to the V
REF
pin, then that voltage is used for the reference. The V
REF
pin should always be bypassed to
ground with a 0.1 µF capacitor close to the reference input pin. Do not load this pin when using the internal
reference.
It is important that all grounds associated with the reference voltage and the analog input signal make connection
to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.
The Reference Bypass Pins (V
RP
, V
CMO
, and V
RN
) for channels A and B are made available for bypass purposes.
These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor
placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between V
RP
and
V
RN
as close to the pins as possible, and a 1 µF capacitor should be placed in parallel. This configuration is
shown in Figure 22. It is necessary to avoid reference oscillation, which could result in reduced SFDR and/or
SNR. V
CMO
may be loaded to 1mA for use as a temperature stable 1.5V reference. The remaining pins should
not be loaded.
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