Datasheet

ADC12C105
www.ti.com SNAS417B –MAY 2007–REVISED AUGUST 2007
DIGITAL INPUTS
Digital CMOS compatible inputs consist of CLK, and PD.
Clock Input
The CLK controls the timing of the sampling process. To achieve the optimum noise performance, the clock input
should be driven with a stable, low jitter clock signal in the range indicated in the Electrical Table. The clock input
signal should also have a short transition region. This can be achieved by passing a low-jitter sinusoidal clock
source through a high speed buffer gate. The trace carrying the clock signal should be as short as possible and
should not cross any other signal line, analog or digital, not even at 90°.
The clock signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the
charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade.
This is what limits the minimum sample rate.
The clock line should be terminated at its source in the characteristic impedance of that line. Take care to
maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905
(SNLA035) for information on setting characteristic impedance.
It is highly desirable that the the source driving the ADC clock pins only drive that pin. However, if that source is
used to drive other devices, then each driven pin should be AC terminated with a series RC to ground, such that
the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is
(6)
where t
PD
is the signal propagation rate down the clock line, "L" is the line length and Z
O
is the characteristic
impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it
as seen from the clock source. Typical t
PD
is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of
"L" and t
PD
should be the same (inches or centimeters).
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise
duty cycle is difficult, the ADC12C105 has a Duty Cycle Stabilizer. It is designed to maintain performance over a
clock duty cycle range of 30% to 70%.
Power-Down (PD)
The PD pin, when high, holds the ADC12C105 in a power-down mode to conserve power when the converter is
not being used. The power consumption in this state is 5 mW if the clock is stopped when PD is high. The output
data pins are undefined and the data in the pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the value of the components on pins 1, 2, and 32 and is
about 3 ms with the recommended components on the V
RP
, V
CMO
and V
RN
reference bypass pins. These
capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before
conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down mode,
but can result in a reduction in SNR, SINAD and ENOB performance.
DIGITAL OUTPUTS
Digital outputs consist of the CMOS signals D0-D11, and DRDY.
The ADC12C105 has 13 CMOS compatible data output pins corresponding to the converted input value and a
data ready (DRDY) signal that should be used to capture the output data. Valid data is present at these outputs
while the PD pin is low. Data should be captured and latched with the rising edge of the DRDY signal.
Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current flows through V
DR
and DRGND. These large charging
current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic
performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will
reduce this problem. The result could be an apparent reduction in dynamic performance.
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