Datasheet

S/H
Stage
11
Stage
1
Stage
2
Stage
3
Stage
n
Stage
9
Stage
10
Timing
Control
11-Stage Pipeline Converter
V
IN+
V
IN-
3 2 2 2 223
3
CLK
Digital Correction
24
V
A
AGND
V
D
DGND
Output
Buffers
Duty
Cycle
Stabilizer
12
D0 - D11
V
DR
14
V
RP
V
RN
V
CMO
Internal
reference
driver
V
REF
DRGND
PD
OF/DCS
Bandgap
reference
DRDY
ADC12C105
(Top View)
1
3
2
4
5
6
7
8
23
24
21
22
20
19
18
17
10
9
12
11
13
14
15
16
32
31
30
29
27
28
26
25
V
RN
V
RP
V
A
AGND
V
REF
V
CMO
AGND
V
A
V
IN
+
V
IN
-
PD
D11 (MSB)
D10
D9
D8
D7
AGND
D6
D5
DRGND
DRDY
V
DR
D4
D3
D2
V
A
CLK
OF/DCS
N/C
N/C
D0
D1
*
ADC12C105
SNAS417B MAY 2007REVISED AUGUST 2007
www.ti.com
Connection Diagram
Block Diagram
2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
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