Datasheet

t
CSH
SCLK
CS
t
CSS
CS
t
CONVERT
t
ACQ
t
CH
t
CL
t
DACC
t
EN
t
DH
t
DS
FOUR ZEROS
DB10
DONTC DONTC ADD2 ADD1 ADD0
DONTC
DONTC DONTC
DB11
DB9 DB8
DB1
1687654321
DB0
DIN
DOUT
SCLK
CS
t
DIS
t
DHLD
8 9 10 11 12 13 14 15 16
Track
Hold
Power Up
ADD2 ADD1 ADD0
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DIN
DOUT
SCLK
CS
Control register
1 2 3 4 5 6 7
1 2 3 4 5 6 7
ADD2 ADD1 ADD0
8
DB11 DB10 DB9
Power
Down
Power Up
Track
Hold
FOUR ZEROS FOUR ZEROS
DB1
DB0
ADC128S102
www.ti.com SNAS298F –AUGUST 2005–REVISED MAY 2013
TIMING DIAGRAMS
Figure 2. ADC128S102 Operational Timing Diagram
Figure 3. ADC128S102 Serial Timing Diagram
Figure 4. SCLK and CS Timing Parameters
Specification Definitions
ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold
capacitor is charged by the input voltage.
APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is
internally acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
CHANNEL-TO-CHANNEL ISOLATION is resistance to coupling of energy from one channel into another
channel.
CROSSTALK is the coupling of energy from one channel into another channel. This is similar to Channel-to-
Channel Isolation, except for the sign of the data.
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