Datasheet
ADC128S102
SNAS298F –AUGUST 2005–REVISED MAY 2013
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ADC128S102 Converter Electrical Characteristics
(1)
(continued)
The following specifications apply for AGND = DGND = 0V, f
SCLK
= 8 MHz to 16 MHz, f
SAMPLE
= 500 ksps to 1 MSPS, C
L
=
50pF, unless otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Limits
Parameter Test Conditions Typical Units
(2)
AC ELECTRICAL CHARACTERISTICS
f
SCLK
MIN Minimum Clock Frequency V
A
= V
D
= +2.7V to +5.25V 0.8 8 MHz (min)
f
SCLK
Maximum Clock Frequency V
A
= V
D
= +2.7V to +5.25V 16 MHz (max)
50 500 ksps (min)
Sample Rate
f
S
V
A
= V
D
= +2.7V to +5.25V
Continuous Mode
1 MSPS (max)
t
CONVERT
Conversion (Hold) Time V
A
= V
D
= +2.7V to +5.25V 13 SCLK cycles
30 40 % (min)
DC SCLK Duty Cycle V
A
= V
D
= +2.7V to +5.25V
70 60 % (max)
t
ACQ
Acquisition (Track) Time V
A
= V
D
= +2.7V to +5.25V 3 SCLK cycles
Acquisition Time + Conversion Time
Throughput Time 16 SCLK cycles
V
A
= V
D
= +2.7V to +5.25V
t
AD
Aperture Delay V
A
= V
D
= +2.7V to +5.25V 4 ns
ADC128S102 Timing Specifications
The following specifications apply for V
A
= V
D
= +2.7V to +5.25V, AGND = DGND = 0V, f
SCLK
= 8 MHz to 16 MHz, f
SAMPLE
=
500 ksps to 1 MSPS, and C
L
= 50pF. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Limits
Parameter Test Conditions Typical Units
(1)
t
CSH
CS Hold Time after SCLK Rising Edge 0 10 ns (min)
t
CSS
CS Setup Time prior to SCLK Rising Edge 4.5 10 ns (min)
t
EN
CS Falling Edge to DOUT enabled 5 30 ns (max)
t
DACC
DOUT Access Time after SCLK Falling Edge 17 27 ns (max)
t
DHLD
DOUT Hold Time after SCLK Falling Edge 4 ns (typ)
t
DS
DIN Setup Time prior to SCLK Rising Edge 3 10 ns (min)
t
DH
DIN Hold Time after SCLK Rising Edge 3 10 ns (min)
0.4 x
t
CH
SCLK High Time ns (min)
t
SCLK
0.4 x
t
CL
SCLK Low Time ns (min)
t
SCLK
DOUT falling 2.4 20 ns (max)
t
DIS
CS Rising Edge to DOUT High-Impedance
DOUT rising 0.9 20 ns (max)
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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