Datasheet

IN0
IN7
MUX T/H
ADC128S102
SCLK
V
A
AGND
DGND
V
D
CS
DIN
DOUT
CONTROL
LOGIC
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
.
.
.
AGND
ADC128S102
SNAS298F –AUGUST 2005–REVISED MAY 2013 www.ti.com
Block Diagram
Pin Descriptions
Pin No. Name Description
ANALOG I/O
4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to V
REF
.
DIGITAL I/O
Digital clock input. The ensured performance range of frequencies for this input is 8 MHz to 16 MHz.
16 SCLK
This clock directly controls the conversion and readout processes.
15 DOUT Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK pin.
Digital data input. The ADC128S102's Control Register is loaded through this pin on rising edges of the
14 DIN
SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as
1 CS
CS is held low.
POWER SUPPLY
Positive analog supply pin. This voltage is also used as the reference voltage. This pin should be
2 V
A
connected to a quiet +2.7V to +5.25V source and bypassed to GND with 1 µF and 0.1 µF monolithic
ceramic capacitors located within 1 cm of the power pin.
Positive digital supply pin. This pin should be connected to a +2.7V to V
A
supply, and bypassed to
13 V
D
GND with a 0.1 µF monolithic ceramic capacitor located within 1 cm of the power pin.
3 AGND The ground return for the analog supply and signals.
12 DGND The ground return for the digital supply and signals.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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