Datasheet

S
SN
S
N
SN
N
C
P
tt
t
P
tt
t
P
+
+
=
xx
+
IN0
IN7
.
.
.
MICROPROCESSOR
DSP
SCLK
CS
DIN
DOUT
AGND
V
A
V
D
ADC128S102
LP2950
5V
0.1 PF
1.0 PF0.1 PF
1 PF0.1 PF
DGND
1.0 PF
51:
22:
INPUT
1 nF
ADC128S102
www.ti.com SNAS298F –AUGUST 2005–REVISED MAY 2013
Applications Information
TYPICAL APPLICATION CIRCUIT
A typical application is shown in Figure 39. The split analog and digital supply pins are both powered in this
example by the TI LP2950 low-dropout voltage regulator. The analog supply is bypassed with a capacitor
network located close to the ADC128S102. The digital supply is separated from the analog supply by an isolation
resistor and bypassed with additional capacitors. The ADC128S102 uses the analog supply (V
A
) as its reference
voltage, so it is very important that V
A
be kept as clean as possible. Due to the low power requirements of the
ADC128S102, it is also possible to use a precision reference as a power supply.
Figure 39. Typical Application Circuit
POWER SUPPLY CONSIDERATIONS
There are three major power supply concerns with this product: power supply sequencing, power management,
and the effect of digital supply noise on the analog supply.
Power Supply Sequence
The ADC128S102 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised
to ensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital
supply (V
D
) cannot exceed the analog supply (V
A
) by more than 300 mV. Therefore, V
A
must ramp up before or
concurrently with V
D
.
Power Management
The ADC128S102 is fully powered-up whenever CS is low and fully powered-down whenever CS is high, with
one exception. If operating in continuous conversion mode, the ADC128S102 automatically enters power-down
mode between SCLK's 16th falling edge of a conversion and SCLK's 1st falling edge of the subsequent
conversion (see Figure 2).
In continuous conversion mode, the ADC128S102 can perform multiple conversions back to back. Each
conversion requires 16 SCLK cycles and the ADC128S102 will perform conversions continuously as long as CS
is held low. Continuous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per
unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this
technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical
specifications. The Power Consumption vs. SCLK curve in the Typical Performance Characteristics section
shows the typical power consumption of the ADC128S102. To calculate the power consumption (P
C
), simply
multiply the fraction of time spent in the normal mode (t
N
) by the normal mode power consumption (P
N
), and add
the fraction of time spent in shutdown mode (t
S
) multiplied by the shutdown mode power consumption (P
S
) as
shown in Equation 3.
(3)
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