Datasheet
8 9 10 11 12 13 14 15 16
Track
Hold
Power Up
ADD2 ADD1 ADD0
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DIN
DOUT
SCLK
CS
Control register
1 2 3 4 5 6 7
1 2 3 4 5 6 7
ADD2 ADD1 ADD0
8
DB11 DB10 DB9
Power
Down
Power Up
Track
Hold
FOUR ZEROS FOUR ZEROS
DB1
DB0
ADC128S052
SNAS333D –AUGUST 2005–REVISED MARCH 2013
www.ti.com
ADC128S052 Converter Electrical Characteristics
(1)
(continued)
The following specifications apply for AGND = DGND = 0V, f
SCLK
= 3.2 MHz to 8 MHz, f
SAMPLE
= 200 kSPS to 500 kSPS, C
L
=
50pF, unless otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits
(2)
Units
50 200 kSPS (min)
Sample Rate
f
S
V
A
= V
D
= +2.7V to +5.25V
Continuous Mode
1000 500 kSPS (max)
t
CONVERT
Conversion (Hold) Time V
A
= V
D
= +2.7V to +5.25V 13 SCLK cycles
30 40 % (min)
DC SCLK Duty Cycle V
A
= V
D
= +2.7V to +5.25V
70 60 % (max)
t
ACQ
Acquisition (Track) Time V
A
= V
D
= +2.7V to +5.25V 3 SCLK cycles
Acquisition Time + Conversion Time
Throughput Time 16 SCLK cycles
V
A
= V
D
= +2.7V to +5.25V
t
AD
Aperture Delay V
A
= V
D
= +2.7V to +5.25V 4 ns
ADC128S052 Timing Specifications
The following specifications apply for V
A
= V
D
= +2.7V to +5.25V, AGND = DGND = 0V, f
SCLK
= 3.2 MHz to 8 MHz, f
SAMPLE
=
200 kSPS to 500 kSPS, and C
L
= 50pF. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits
(1)
Units
t
CSH
CS Hold Time after SCLK Rising Edge 0 10 ns (min)
CS Setup Time prior to SCLK Rising
t
CSS
4.5 10 ns (min)
Edge
t
EN
CS Falling Edge to DOUT enabled 5 30 ns (max)
DOUT Access Time after SCLK Falling
t
DACC
17 27 ns (max)
Edge
DOUT Hold Time after SCLK Falling
t
DHLD
4 ns (typ)
Edge
DIN Setup Time prior to SCLK Rising
t
DS
3 10 ns (min)
Edge
t
DH
DIN Hold Time after SCLK Rising Edge 3 10 ns (min)
t
CH
SCLK High Time 0.4 x t
SCLK
ns (min)
t
CL
SCLK Low Time 0.4 x t
SCLK
ns (min)
DOUT falling 2.4 20 ns (max)
CS Rising Edge to DOUT High-
t
DIS
Impedance
DOUT rising 0.9 20 ns (max)
(1) Tested limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
Timing Diagrams
Figure 1. ADC128S052 Operational Timing Diagram
6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: ADC128S052