Datasheet

IN0
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
IN7
V
A
/2
IN0
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
V
A
/2
SW2
IN7
ADC128S052
SNAS333D –AUGUST 2005–REVISED MARCH 2013 www.ti.com
FUNCTIONAL DESCRIPTION
The ADC128S052 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter.
ADC128S052 OPERATION
Simplified schematics of the ADC128S052 in both track and hold operation are shown in Figure 34 and Figure 35
respectively. In Figure 34, the ADC128S052 is in track mode: switch SW1 connects the sampling capacitor to
one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The
ADC128S052 is in this state for the first three SCLK cycles after CS is brought low.
Figure 35 shows the ADC128S052 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until
the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC128S052 is in this state for the last thirteen SCLK cycles
after CS is brought low.
Figure 34. ADC128S052 in Track Mode
Figure 35. ADC128S052 in Hold Mode
SERIAL INTERFACE
An operational timing diagram and a serial interface timing diagram for the ADC128S052 are shown in the
Timing Diagrams. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock)
controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a
conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC128S052's Control
Register is placed on DIN, the serial data input pin. New data is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high
and is active when CS is low. Thus, CS acts as an output enable. Similarly, SCLK is internally gated off when CS
is brought high.
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