Datasheet

500.0 1.2k 1.9k 2.7k 3.4k 4.1k
CODE
TUE (%)
-0.020
-0.060
-0.100
-0.140
-0.180
-0.220
500.0 1.2k 1.9k 2.7k 3.4k 4.1k
CODE
TUE (%)
-0.020
-0.064
-0.108
-0.152
-0.196
-0.240
500.0 1.2k 1.9k 2.7k 3.4k 4.1k
CODE
TUE (%)
0.023
0.014
0.004
-0.005
-0.015
-0.024
500.0 1.2k 1.9k 2.7k 3.4k 4.1k
CODE
TUE (%)
-0.010
-0.074
-0.138
-0.202
-0.266
-0.330
ADC128D818
www.ti.com SNAS483E –FEBRUARY 2010–REVISED MARCH 2013
Typical Performance Characteristics
The following typical performance plots apply for the internal VREF = 2.56V, V+ = 3.3V, Pseudo-Differential connection,
unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25°C.
(1)
TUE vs. Code TUE vs. Code (External VREF = 1.25V)
Figure 2. Figure 3.
TUE vs. Code (External VREF = 2.56V) TUE vs. Code (External VREF = 5V, V+ = 5V)
Figure 4. Figure 5.
INL vs. Code (External VREF = 1.25V for 1 Unit) INL vs. Code (External VREF = 1.25V for 28 Units)
Figure 6. Figure 7.
(1) Timing specifications are tested at the Serial Bus Input logic levels: V
IN(0)
= 0.3 × V
+
for a falling edge and V
IN(1)
= 0.7 × V
+
for a rising
edge if the SCL and SDA edge rates are similar.
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