Datasheet

IN0 Watchdog
Interrupt
Status
Registers
Interrupt
Mask
Registers
IN1 Watchdog
IN2 Watchdog
IN3 Watchdog
IN4 Watchdog
IN5 Watchdog
IN6 Watchdog
IN7 Watchdog
TEMP Watchdog
INT_Clear
(00h[3])
INT
Enable
(00h[1])
INT
ADC128D818
SNAS483E –FEBRUARY 2010–REVISED MARCH 2013 www.ti.com
Digital Code
Temp Limit
Binary [MSb...LSb] Decimal Hex
+0°C 0000_0000 0 00
−1.0°C 1111_1111 255 FF
−25°C 1110_1111 231 E7
−40°C 1101_1000 216 D8
INTERRUPT STRUCTURE
Figure 34. Interrupt Structure
Figure 34 shows the ADC128D818's Interrupt Structure. Note that the number next to each bit name represents
its register address and bit number. For example, 'INT_Clear' (00h[3]) refers to bit 3 of register address 00h.
Interrupt Output (INT)
ADC128D818 generates an interrupt as a result of each of its internal WATCHDOG registers on the voltage and
temperature channels. In general, INT becomes active when all three scenarios, as depicted in Figure 34, occur:
1. 'INT_Clear' (00h[3]) = 0.
2. 'INT_Enable' (00h[1]) = 1 to enable interrupt output.
3. The voltage reading > the voltage high limit or ≤ the voltage low limit, or the temperature reading > T
hot
.
Interrupt Clearing
Reading the Interrupt Status Register (addresses 01h) will output the contents of the register and clear the
register. When the Interrupt Status Register clears, the interrupt output pin, INT, also clears until this register is
updated by the round-robin monitoring loop.
Another method to clear the interrupt output pin, INT, is setting 'INT_Clear' bit (address 00h, bit 3) = 1. When this
bit is high, the ADC128D818 round-robin monitoring loop will stop.
Temperature Interrupt
One of the ADC128D818 features is monitoring the temperature reading. This monitoring is accomplished by
setting a temperature limit to the Temperature High Limit Register (T
hot
, address 38h) and Temperature
Hysteresis Limit Register (T
hot_hyst
, address 39h). These limit registers have an interrupt mode, shown in
Figure 35, that operates the the following way: if the temperature reading > T
hot
, an interrupt will occur and will
remain active indefinitely until reset by reading the Interrupt Status Register (address 01h) or cleared by the
'INT_Clear' bit.
Once an interrupt event has occurred by crossing T
hot
, then reset, an interrupt will occur again once the next
temperature conversion has completed. The interrupts will continue to occur in this manner until the temperature
reading is ≤ T
hot_hyst
and a read of the Interrupt Status Register has occurred.
22 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: ADC128D818