Datasheet

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8
Track Hold
Power Up
Track Hold
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
9 10
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB11 DB10 DB9 DB8 DB7
DIN
DOUT
Power Up
SCLK
CS
Power Down
Control register
Control register
ADC124S051
SNAS260E –NOVEMBER 2004–REVISED NOVEMBER 2004 www.ti.com
ADC124S051 Timing Specifications
The following specifications apply for V
A
= +2.7V to 5.25V, GND = 0V, f
SCLK
= 3.2 MHz to 8 MHz, f
SAMPLE
= 200 to 500 ksps,
C
L
= 35 pF, Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits
(1)
Units
V
A
= +3.0V −3.5
t
CSU
Setup Time SCLK High to CS Falling Edge See
(2)
10 ns (min)
V
A
= +5.0V −0.5
V
A
= +3.0V +4.5
t
CLH
Hold time SCLK Low to CS Falling Edge See
(2)
10 ns (min)
V
A
= +5.0V +1.5
V
A
= +3.0V +4
t
EN
Delay from CS Until DOUT active 30 ns (max)
V
A
= +5.0V +2
V
A
= +3.0V +14.5
t
ACC
Data Access Time after SCLK Falling Edge 30 ns (max)
V
A
= +5.0V +13
t
SU
Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min)
t
H
Data Valid SCLK Hold Time +3 10 ns (min)
0.3 x
t
CH
SCLK High Pulse Width 0.5 x t
SCLK
ns (min)
t
SCLK
0.3 x
t
CL
SCLK Low Pulse Width 0.5 x t
SCLK
ns (min)
t
SCLK
V
A
= +3.0V 1.8
Output Falling
V
A
= +5.0V 1.3
t
DIS
CS Rising Edge to DOUT High-Impedance 20 ns (max)
V
A
= +3.0V 1.0
Output Rising
V
A
= +5.0V 1.0
(1) Tested limits are ensured to AOQL (Average Outgoing Quality Level).
(2) Clock may be either high or low when CS is asserted as long as setup and hold times t
CSU
and t
CLH
are strictly observed..
Timing Diagrams
Figure 1. ADC124S051 Operational Timing Diagram
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