Datasheet

IN1
IN4
MUX
T/H
SCLK
V
A
GND
CS
DIN
DOUT
CONTROL
LOGIC
12-Bit
SUCCESSIVE
APPROXIMATION
ADC
.
.
.
GND
ADC124S051
SNAS260E –NOVEMBER 2004–REVISED NOVEMBER 2004 www.ti.com
Block Diagram
PIN DESCRIPTIONS and EQUIVALENT CIRCUITS
Pin No. Symbol Description
ANALOG I/O
4-7 IN1 to IN4 Analog inputs. These signals can range from 0V to V
A
.
DIGITAL I/O
10 SCLK Digital clock input. This clock directly controls the conversion and readout processes.
Digital data output. The output samples are clocked out of this pin on falling edges of the
9 DOUT
SCLK pin.
Digital data input. The ADC124S051's Control Register is loaded through this pin on rising
8 DIN
edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue
1 CS
as long as CS is held low.
POWER SUPPLY
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and
2 V
A
bypassed to GND with a 1 µF tantalum capacitor and a 0.1 µF ceramic monolithic capacitor
located within 1 cm of the power pin.
3 GND The ground return for the supply and signals.
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