Datasheet

IN1
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
IN4
2
V
A
IN1
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
IN4
2
V
A
ADC124S051
www.ti.com SNAS260E –NOVEMBER 2004–REVISED NOVEMBER 2004
APPLICATIONS INFORMATION
ADC124S051 OPERATION
The ADC124S051 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter. Simplified schematics of the ADC124S051 in both track and hold modes
are shown in Figure 47 Figure 48, respectively. In Figure 47, the ADC124S051 is in track mode: switch SW1
connects the sampling capacitor to one of four analog input channels through the multiplexer, and SW2 balances
the comparator inputs. The ADC124S051 is in this state for the first three SCLK cycles after CS is brought low.
Figure 48 shows the ADC124S051 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is
balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of
the analog input voltage. The ADC124S051 is in this state for the fourth through sixteenth SCLK cycles after CS
is brought low.
The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of
16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is
clocked into the DIN pin to indicate the multiplexer address for the next conversion.
Figure 47. ADC124S051 in Track Mode
Figure 48. ADC124S051 in Hold Mode
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