Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply VSSOP 10

CS SCLK

DOUT

DIN

IN1

GND

IN4

IN3 IN2

ADC124S051

www.ti.com

SNAS260E –NOVEMBER 2004–REVISED NOVEMBER 2004

ADC124S051 4 Channel, 200 ksps to 500 ksps, 12-Bit A/D Converter

Check for Samples: ADC124S051

FEATURES

DESCRIPTION

The ADC124S051 is a low-power, four-channel

• Specified Over a Range of Sample Rates

CMOS 12-bit analog-to-digital converter with a high-

• Four Input Channels

speed serial interface. Unlike the conventional

• Variable Power Management

practice of specifying performance at a single sample

rate only, the ADC124S051 is fully specified over a

• Single Power Supply with 2.7V - 5.25V Range

sample rate range of 200 ksps to 500 ksps. The

converter is based on a successive-approximation

KEY SPECIFICATIONS

• DNL: +0.7 / −0.4 LSB (typ)

circuit. It can be configured to accept up to four input

signals at inputs IN1 through IN4.

• INL: ± 0.5 LSB (typ)

• SNR: 72.5 dB (typ)

The output serial data is straight binary, and is

compatible with several standards, such as SPI™,

• Power Consumption:

QSPI™, MICROWIRE and many common DSP serial

– 3V Supply: 3.0 mW (typ)

interfaces.

– 5V Supply: 10.0 mW (typ)

The ADC124S051 operates with a single supply that

can range from +2.7V to +5.25V. Normal power

APPLICATIONS

consumption using a +3V or +5V supply is 3.0 mW

• Portable Systems

and 10.0 mW, respectively. The power-down feature

reduces the power consumption to just 0.14 µW using

• Remote Data Acquisition

a +3V supply, or 0.32 µW using a +5V supply.

• Instrumentation and Control Systems

The ADC124S051 is packaged in a 10-lead VSSOP

package. Operation over the industrial temperature

range of −40°C to +85°C is ensured.

Table 1. Pin-Compatible Alternatives by Resolution and Speed

(1)

Resolution Specified for a Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC124S021 ADC124S051 ADC122S101

10-bit ADC104S021 ADC104S051 ADC102S101

8-bit ADC084S021 ADC084S051 ADC082S101

(1) All devices are fully pin and function compatible.

Connection Diagram

10 Pin VSSOP Package

See Package Number DGS

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

PAGE 1
ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 ADC124S051 4 Channel, 200 ksps to 500 ksps, 12-Bit A/D Converter Check for Samples: ADC124S051 FEATURES DESCRIPTION • • • • The ADC124S051 is a low-power, four-channel CMOS 12-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC124S051 is fully specified over a sample rate range of 200 ksps to 500 ksps.
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ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com Block Diagram IN1 . . . MUX IN4 T/H 12-Bit SUCCESSIVE APPROXIMATION ADC VA CONTROL LOGIC CS GND GND SCLK DIN DOUT PIN DESCRIPTIONS and EQUIVALENT CIRCUITS Pin No. Symbol Description ANALOG I/O 4-7 IN1 to IN4 Analog inputs. These signals can range from 0V to VA. DIGITAL I/O 10 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 9 DOUT Digital data output.
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ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Supply Voltage VA −0.3V to VA +0.
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ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com ADC124S051 Converter Electrical Characteristics (1) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 to 500 ksps, CL = 35 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits (2) Units STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes 12 Bits ±0.5 ±1.
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ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 ADC124S051 Converter Electrical Characteristics(1) (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 to 500 ksps, CL = 35 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Limits Typical (2) Units VA − 0.5 V (min) 0.4 V (max) 0.
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ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com ADC124S051 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 to 500 ksps, CL = 35 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical VA = +3.0V −3.5 VA = +5.0V −0.5 VA = +3.0V +4.5 VA = +5.0V +1.5 VA = +3.0V +4 VA = +5.0V +2 VA = +3.0V +14.5 VA = +5.
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ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 IOL 200 PA To Output Pin 1.6V CL 35 pF IOH 200 PA Figure 2. Timing Test Circuit CS tACQ tCONVERT tCH SCLK 1 2 3 4 6 DOUT Z3 tSU Z2 Z1 7 8 16 tACC tCL tEN DIN 5 Z0 DB11 DB10 tDIS DB9 DB1 DB8 DB0 tH DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Figure 3. ADC124S051 Serial Timing Diagram CS tCSU SCLK tCLH SCLK Figure 4.
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ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion.
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ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as: THD = 20 ‡ log10 A f 22 + + A f 62 A f12 where • • Af1 is the RMS power of the input frequency at the output and A Af2 through f6 are the RMS power in the first 5 harmonic frequencies.
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ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 10 DNL - VA = 3.0V INL - VA = 3.0V Figure 5. Figure 6. DNL - VA = 5.0V INL - VA = 5.0V Figure 7. Figure 8. DNL vs. Supply INL vs. Supply Figure 9. Figure 10.
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ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. DNL vs. Clock Frequency INL vs. Clock Frequency Figure 11. Figure 12. DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle Figure 13. Figure 14. DNL vs. Temperature INL vs. Temperature Figure 15. Figure 16.
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ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 12 SNR vs. Supply THD vs. Supply Figure 17. Figure 18. SNR vs. Clock Frequency THD vs. Clock Frequency Figure 19. Figure 20. SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle Figure 21. Figure 22.
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ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. SNR vs. Input Frequency THD vs. Input Frequency Figure 23. Figure 24. SNR vs. Temperature THD vs. Temperature Figure 25. Figure 26. SFDR vs. Supply SINAD vs. Supply Figure 27. Figure 28.
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ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 14 SFDR vs. Clock Frequency SINAD vs. Clock Frequency Figure 29. Figure 30. SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle Figure 31. Figure 32. SFDR vs. Input Frequency SINAD vs. Input Frequency Figure 33. Figure 34.
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ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. SFDR vs. Temperature SINAD vs. Temperature Figure 35. Figure 36. ENOB vs. Supply ENOB vs. Clock Frequency Figure 37. Figure 38. ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency Figure 39. Figure 40.
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ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 16 ENOB vs. Temperature Spectral Response - 3V, 200 ksps Figure 41. Figure 42. Spectral Response - 5V, 200 ksps Spectral Response - 3V, 500 ksps Figure 43. Figure 44. Spectral Response - 5V, 500 ksps Power Consumption vs. Throughput Figure 45. Figure 46.
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ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 APPLICATIONS INFORMATION ADC124S051 OPERATION The ADC124S051 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. Simplified schematics of the ADC124S051 in both track and hold modes are shown in Figure 47 Figure 48, respectively.
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ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com USING THE ADC124S051 An ADC124S051 timing diagram and a serial interface timing diagram for the ADC124S051 are shown in the Timing Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first.
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ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 ADC124S051 TRANSFER FUNCTION The output format of the ADC124S051 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC124S051 is VA/4096. The ideal transfer characteristic is shown in Figure 49. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA/8192. Other code transitions occur at steps of one LSB. 111...
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ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com ANALOG INPUTS An equivalent circuit for one of the ADC124S051's input channels is shown in Figure 51. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time should any input go beyond (VA + 300 mV) or (GND − 300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. For this reason, these ESD diodes should NOT be used to clamp the input signal.
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ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 Power Management When the ADC124S051 is operated continuously in normal mode, the maximum throughput is fSCLK/16. Throughput may be traded for power consumption by running fSCLK at its maximum 8 MHz and performing fewer conversions per unit time, putting the ADC124S051 into shutdown mode between conversions. A plot of typical Power Consumption vs. Throughput is shown in the Typical Performance Characteristics section.
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ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E • 22 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC124S051CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC124S051CIMMX/NOP VSSOP B DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC124S051CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 VSSOP DGS 10 3500 367.0 367.0 35.
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