Datasheet

D
OUT
CS
V
IH
t
DIS
90%
10%
90%
10%
D
OUT
90%
10%
SCLK
CS
t
CSSU
1 2
V
IL
2.4V
0.8V
D
OUT
SCLK
t
DH
t
DA
D
OUT
t
f
t
r
2.4V
0.8V
D
OUTB
SCLK
CS
t
CONV
MSB
t
ACQ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
HI-Z
DB10 DB9 DB8 DB7 DB6DB11 DB5 DB4 DB3 DB2 DB1 DB0
LSB
t
CONV
t
ACQ
3 4 5 61 2 7 8
MSB
DB10 DB9 DB8DB11
D
OUTA
MSB
HI-Z
DB10 DB9 DB8 DB7 DB6DB11 DB5 DB4 DB3 DB2 DB1 DB0
LSB
MSB
DB10 DB9 DB8DB11
t
PD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
t
ACQ
t
CONV
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DOUTA
SCLK
CS
4 Leading Zeroes
17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
t
Power Down
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DOUTA
SCLK
CS
4 Leading Zeroes
Channel A Data
Channel B Data
ADC122S706
SNAS408A –NOVEMBER 2007–REVISED MARCH 2013 www.ti.com
Figure 2. ADC122S706 Single Conversion Timing Diagram (SINGLE Data Output Mode)
Figure 3. ADC122S706 Continuous Conversion Timing Diagram (DUAL Data Output Mode)
Figure 4. D
OUT
Rise and Fall Times Figure 5. D
OUT
Hold and Access Times
Figure 6. Valid CS Assertion Times Figure 7. Voltage Waveform for t
DIS
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