Datasheet

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
t
ACQ
t
CONV
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DOUTA
SCLK
CS
4 Leading Zeroes
t
PD
Channel A Data
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DOUTB
4 Leading Zeroes
Channel B Data
t
EN
t
DIS
t
CL
t
CH
ADC122S706
www.ti.com SNAS408A –NOVEMBER 2007–REVISED MARCH 2013
ADC122S706 Timing Specifications
(1)
The following specifications apply for V
A
= +4.5V to 5.5V, V
D
= +2.7V to V
A
, V
REF
= 2.5V, f
SCLK
= 8 MHz to 16 MHz, C
L
= 25
pF, unless otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits Units
5 11 ns (min)
V
D
= +2.7V to 3.6V
1/ f
SCLK
1/ f
SCLK
- 3 ns (max)
t
CSSU
CS Setup Time prior to an SCLK rising edge
4 7 ns (min)
V
D
= +4.5V to 5.5V
1/ f
SCLK
1/ f
SCLK
- 3 ns (max)
V
D
= +2.7V to 3.6V 22 39 ns (max)
t
EN
D
OUT
Enable Time after the falling edge of CS
V
D
= +4.5V to 5.5V 9 20 ns (max)
t
DH
D
OUT
Hold time after an SCLK Falling edge 9 6 ns (min)
V
D
= +2.7V to 3.6V 24 39 ns (max)
t
DA
D
OUT
Access time after an SCLK Falling edge
V
D
= +4.5V to 5.5V 20 26 ns (max)
t
DIS
D
OUT
Disable Time after the rising edge of CS
(2)
10 20 ns (max)
t
CH
SCLK High Time 25 ns (min)
t
CL
SCLK Low Time 25 ns (min)
t
r
D
OUT
Rise Time 7 ns
t
f
D
OUT
Fall Time 7 ns
(1) Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
(2) t
DIS
is the time for D
OUT
to change 10%.
Timing Diagrams
Figure 1. ADC122S706 Single Conversion Timing Diagram (DUAL Data Output Mode)
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