Datasheet

ADC122S706
www.ti.com
SNAS408A NOVEMBER 2007REVISED MARCH 2013
ADC122S706 Converter Electrical Characteristics
(1)
The following specifications apply for V
A
= +4.5V to 5.5V, V
D
= +2.7V to V
A
, V
REF
= 2.5V, f
SCLK
= 8 to 16 MHz, DUAL = V
D
, f
IN
= 100 kHz, C
L
= 25 pF, unless otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
; all other limits are at T
A
= 25°C.
Symbol Parameter Conditions Typical Limits Units
(2)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits
Integral Non-Linearity ±0.5 ±1 LSB (max)
INL
Integral Non-Linearity Matching 0.02 LSB
Differential Non-Linearity ±0.4 ±0.95 LSB (max)
DNL
Differential Non-Linearity Matching 0.02 LSB
Offset Error 0.2 ±3 LSB (max)
OE
Offset Error Matching 0.1 LSB
Positive Gain Error 2 ±5 LSB (max)
Positive Gain Error Matching 0.2 LSB
GE
Negative Gain Error 3 ±8 LSB (max)
Negative Gain Error Matching 0.2 LSB
DYNAMIC CONVERTER CHARACTERISTICS
SINAD Signal-to-Noise Plus Distortion Ratio f
IN
= 100 kHz, 0.1 dBFS 72.5 69.5 dBc (min)
SNR Signal-to-Noise Ratio f
IN
= 100 kHz, 0.1 dBFS 73.2 71 dBc (min)
THD Total Harmonic Distortion f
IN
= 100 kHz, 0.1 dBFS 83 72 dBc (max)
SFDR Spurious-Free Dynamic Range f
IN
= 100 kHz, 0.1 dBFS 84 72 dBc (min)
ENOB Effective Number of Bits f
IN
= 100 kHz, 0.1 dBFS 11.8 11.25 bits (min)
Differential Input 26 MHz
Output at 70.7%FS
FPBW 3 dB Full Power Bandwidth
with FS Input
Single-Ended Input 22 MHz
ISOL Channel-to-Channel Isolation f
IN
< 1 MHz 90 dBc
ANALOG INPUT CHARACTERISTICS
V
REF
V (min)
V
IN
Differential Input Range
+V
REF
V (max)
I
DCL
DC Leakage Current V
IN
= V
REF
or V
IN
= -V
REF
±1 µA (max)
In Track Mode 20 pF
C
INA
Input Capacitance
In Hold Mode 3 pF
CMRR Common Mode Rejection Ratio See Specification Definitions 90 dB
1.0 V (min)
V
REF
Reference Voltage Range
V
A
V (max)
DIGITAL INPUT CHARACTERISTICS
V
IH
Input High Voltage 2.4 V (min)
V
IL
Input Low Voltage 0.8 V (max)
I
IN
Input Current
(3)
V
IN
= 0V or V
A
±1 µA (max)
C
IND
Input Capacitance 2 4 pF (max)
DIGITAL OUTPUT CHARACTERISTICS
I
SOURCE
= 200 µA V
D
0.02 V
D
0.2 V (min)
V
OH
Output High Voltage
I
SOURCE
= 1 mA V
D
0.09 V
I
SINK
= 200 µA 0.01 0.4 V (max)
V
OL
Output Low Voltage
I
SINK
= 1 mA 0.08 V
I
OZH
, I
OZL
TRI-STATE Leakage Current Force 0V or V
A
±1 µA (max)
C
OUT
TRI-STATE Output Capacitance Force 0V or V
A
2 4 pF (max)
Output Coding Binary 2'S Complement
(1) Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
(2) Tested limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
(3) The digital input pin, DUAL, has a leakage current of ±5 µA.
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