Datasheet

ADC122S706
www.ti.com SNAS408A –NOVEMBER 2007–REVISED MARCH 2013
PIN DESCRIPTIONS
Pin No. Symbol Description
Voltage Reference Input. A voltage reference between 1V and V
A
must be applied to this
input. V
REF
must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF.
1 V
REF
A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended for
enhanced performance.
Non-Inverting Input for Channel A. CHA+ is the positive analog input for the differential
2 CHA+
signal applied to Channel A.
Inverting Input for Channel A. CHA− is the negative analog input for the differential signal
3 CHA−
applied to Channel A.
4 GND Ground. GND is the ground reference point for all signals applied to the ADC122S706.
Inverting Input for Channel B. CHB− is the negative analog input for the differential signal
5 CHB−
applied to Channel B.
Non-Inverting Input for Channel B. CHB+ is the positive analog input for the differential
6 CHB+
signal applied to Channel B.
Analog Power Supply input. A voltage source between 4.5V and 5.5V must be applied to
7 V
A
this input. V
A
must be decoupled to GND with a ceramic capacitor value of 0.1 µF in
parallel with a bulk capacitor value of 1.0 µF to 10 µF.
Applying a logic high to this pin causes the conversion result of Channel A to be output on
D
OUTA
and the conversion result of Channel B to be output on D
OUTB
. Grounding this pin
8 DUAL
causes the conversion result of Channel A and B to be output on D
OUTA
, with the result of
Channel A being output first. D
OUTB
is in a high impedance state when DUAL is grounded.
9 GND Ground. GND is the ground reference point for all signals applied to the ADC122S706.
Digital Power Supply input. A voltage source between 2.7V and V
A
must be applied to this
10 V
D
input. V
D
must be decoupled to GND with a ceramic capacitor value of 0.1 µF in parallel
with a bulk capacitor value of 1.0 µF to 10 µF.
Serial Data Output for Channel A. With DUAL at a logic high state, the conversion result for
Channel A is provided on D
OUTA
. The serial data output word is comprised of 4 null bits and
11 D
OUTA
12 data bits (MSB first). During a conversion, the data is outputted on the falling edges of
SCLK and is generally valid on the rising edges. With DUAL at a logic low state, the
conversion result of Channel A and B is outputted on D
OUTA
.
Serial Data Output for Channel B. With DUAL at a logic high state, the conversion result for
Channel B is provided on D
OUTB
. The serial data output word is comprised of 4 null bits and
12 D
OUTB
12 data bits (MSB first). During a conversion, the data is outputted on the falling edges of
SCLK and is generally valid on the rising edges. With DUAL at a logic low state, D
OUTB
is in
a high impedance state.
13 SCLK Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.
Chip Select Bar. CS is active low. The ADC122S706 is in Normal Mode when CS is LOW
14 CS
and Power-Down Mode when CS is HIGH. A conversion begins on the fall of CS.
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