Datasheet

ADC122S706
www.ti.com
SNAS408A NOVEMBER 2007REVISED MARCH 2013
Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC122S706:
40°C T
A
+105°C
+4.5V V
A
+5.5V
+2.7V V
D
V
A
1V V
REF
V
A
8 MHz f
SCLK
16 MHz
V
CM
: See Input Common Mode Voltage
POWER CONSUMPTION
The architecture, design, and fabrication process allow the ADC122S706 to operate at conversion rates up to 1
MSPS while consuming very little power. The ADC122S706 consumes the least amount of power while operating
in power down mode. For applications where power consumption is critical, the ADC122S706 should be
operated in power down mode as often as the application will tolerate. To further reduce power consumption,
stop the SCLK while CS is high.
Short Cycling
Short cycling refers to the process of halting a conversion after the last needed bit is outputted. Short cycling can
be used to lower the power consumption in those applications that do not need a full 12-bit resolution, or where
an analog signal is being monitored until some condition occurs. For example, it may not be necessary to use the
full 12-bit resolution of the ADC122S706 as long as the signal being monitored is within certain limits. In some
circumstances, the conversion could be terminated after the first few bits. This will lower power consumption in
the converter since the ADC122S706 spends more time in power down mode and less time in the conversion
mode.
Short cycling is accomplished by pulling CS high after the last required bit is received from the ADC122S706
output. This is possible because the ADC122S706 places the latest converted data bit on D
OUT
as it is
generated. If only 8-bits of the conversion result are needed, for example, the conversion can be terminated by
pulling CS high after the 8th bit has been clocked out.
Burst Mode Operation
Normal operation of the ADC122S706 requires the SCLK frequency to be sixteen times the sample rate and the
CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications
requiring sample rates below 500 kSPS, the ADC122S706 should be run with an SCLK frequency of 16 MHz and
a CS rate as slow as the system requires. When this is accomplished, the ADC122S706 is operating in burst
mode. The ADC122S706 enters into power down mode at the end of each conversion, minimizing power
consumption. This causes the converter to spend the longest possible time in power down mode. Since power
consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest
conversion rate that will satisfy the requirements of the system.
Single DOUT mode
With the DUAL pin connected to a logic low level, the ADC122S706 is operating in single DOUT mode. In single
DOUT mode, the conversion result of Channel A and Channel B are both output on D
OUTA
(see Figure 2).
Operating in this mode causes the maximum conversion rate to be reduced to 500kSPS while operating with an
SCLK frequency of 16 MHz. This is a result of the conversion window changing from 16 clock cycles to 32 clock
cycles to receive the conversion result of Channel A and Channel B. Since the conversion of Channel A and
Channel B are still performed simultaneously, the ADC122S706 still enters a power down state on the 16th
falling edge of SCLK. The increased time spent in power down mode causes the power consumption of the
ADC122S706 to reduce nearly by a factor of two. See the Power Supply Characteristics Table for more details.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: ADC122S706