Datasheet

ADC122S706
SNAS408A –NOVEMBER 2007–REVISED MARCH 2013 www.ti.com
CS Input
The CS (chip select bar) is an active low input that is TTL and CMOS compatible. The ADC122S706 is in
conversion mode when CS is low and power-down mode when CS is high. As a result, CS frames the
conversion window. The falling edge of CS marks the beginning of a conversion and the rising edge of CS marks
the end of a conversion window. Multiple conversions can occur within a given conversion frame with each
conversion requiring sixteen SCLK cycles. This is referred to as continuous conversion mode and is shown in
Figure 3 of Timing Diagrams.
Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS
occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is
clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature,
and characteristics of the individual device. To ensure that the MSB is always clocked out at a given time (the
5th falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in
Timing Specifications.
SCLK Input
The SCLK (serial clock) serves two purposes in the ADC122S706. It is used by the ADC as the conversion clock
and it is used as the serial clock to output the conversion results. This SCLK input is CMOS compatible. Internal
settling time requirements limit the maximum clock frequency while internal capacitor leakage limits the minimum
clock frequency. The ADC122S706 offers guaranteed performance with the clock rates indicated in the electrical
table.
Data Output(s)
The ADC122S706 enables system designers two options for receiving converted data from the ADC122S706.
Data can be received from separate data output pins (D
OUTA
and D
OUTB
) or from a single data output line. These
options are controlled by the digital input pin DUAL. With the DUAL pin set to a logic high level, the dual high-
speed serial outputs are enabled. Channel A's conversion result is outputted on D
OUTA
while Channel B's
conversion result is outputted on D
OUTB
. With the DUAL pin set to a logic low level, the conversion result of
Channel A and Channel B is outputted on D
OUTA
, with the result of Channel A being outputted before the result of
Channel B. The D
OUTB
pin is in a high impedance state during this condition. See Figure 1 and Figure 2 in Timing
Diagrams for more details on DUAL and SINGLE DOUT mode.
The output data format of the ADC122S706 is two’s complement, as shown in Table 2. This table indicates the
ideal output code for the given input voltage and does not include the effects of offset, gain error, linearity errors,
or noise. Each data bit is output on the falling edge of SCLK.
Table 2. Ideal Output Code vs. Input Voltage
Analog Input, (+IN) − (−IN) 2's Complement Binary Output 2's Comp. Hex Code 2's Comp. Dec Code
V
REF
− 1.5 LSB 0111 1111 1111 7FF 2047
+ 0.5 LSB 0000 0000 0001 001 1
− 0.5 LSB 0000 0000 0000 000 0
0V − 1.5 LSB 1111 1111 1111 FFF −1
−V
REF
+ 0.5 LSB 1000 0000 0000 800 −2048
While data is output on the falling edges of SCLK, receiving systems have the option of capturing the data on the
subsequent rising or falling edge of SCLK. The maximum specification for t
DA
(D
OUT
access time after an SCLK
falling edge) is provided for two power supply ranges. If the system is operating at the maximum clock frequency
of 16 MHz and a V
D
supply voltage of 3V, it would be necessary for the receiver to capture data on the
subsequent falling edge of SCLK in order to guarantee performance over the entire temperature range.
Operating at a V
D
supply voltage of 5V or an SCLK frequency less than 10 MHz allows data to be captured on
either edge of SCLK. If a receiving system is going to capture data on the subsequent falling edge of SCLK, it is
important to make sure that the minimum hold time after an SCLK falling edge (t
DH
) is acceptable. See Figure 5
for D
OUT
hold and access times.
D
OUT
is enabled on the falling edge of CS and disabled on the rising edge of CS. If CS is raised prior to the 16th
falling edge of SCLK, the current conversion is aborted and D
OUT
will go into its high impedance state. A new
conversion will begin when CS is taken LOW.
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