Datasheet

Differential Input
1.25
0.0 1.0 2.0 3.0 4.0 5.0
3.75
V
A
= 5.0V
V
REF
(V)
COMMON-MODE VOLTAGE (V)
2.5
0
5
-1
6
2.5
Single-Ended Input
1.25
0.0 0.75 1.75 2.5
3.75
V
A
= 5.0V
V
REF
(V)
COMMON-MODE VOLTAGE (V)
2.5
0
5
-1
6
1.25
ADC122S706
www.ti.com SNAS408A –NOVEMBER 2007–REVISED MARCH 2013
Input Common Mode Voltage
The allowable input common mode voltage (V
CM
) range depends upon the supply and reference voltages used
for the ADC122S706. The ranges of V
CM
are depicted in Figure 46 and Figure 47. Equations for calculating the
minimum and maximum common mode voltages for differential and single-ended operation are shown in
Table 1.
Figure 46. V
CM
range for Differential Input Figure 47. V
CM
range for single-ended operation
operation
Table 1. Allowable V
CM
Range
Input Signal Minimum V
CM
Maximum V
CM
Differential V
REF
/ 2 V
A
− V
REF
/ 2
Single-Ended V
REF
V
A
− V
REF
SERIAL DIGITAL INTERFACE
The ADC122S706 communicates via a synchronous serial interface as shown in Timing Diagrams. CS, chip
select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion
process and the timing of the serial data. D
OUTA
and D
OUTB
are the serial data output pins, where the conversion
results of Channel A and Channel B are sent as serial data streams, MSB first.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC122S706's data
output pins are in a high impedance state when CS is high and are active when CS is low; thus CS acts as an
output enable. A timing diagram for a single conversion is shown in Figure 1.
During the first three cycles of SCLK, the ADC122S706 is in acquisition mode (t
ACQ
), tracking the input voltage.
For the next twelve SCLK cycles (t
CONV
), the conversion is accomplished and the data is clocked out. SCLK
falling edges one through four clock out leading zeros while falling edges five through sixteen clock out the
conversion result, MSB first. If there is more than one conversion in a frame (continuous conversion mode), the
ADC122S706 will re-enter acquisition mode on the falling edge of SCLK after the N*16th rising edge of SCLK
and re-enter the conversion mode on the N*16+4th falling edge of SCLK as shown in Figure 3. "N" is an integer
value.
The ADC122S706 can enter acquisition mode under three different conditions. The first condition involves CS
going low (asserted) with SCLK high. In this case, the ADC122S706 enters acquisition mode on the first falling
edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this condition,
the ADC122S706 automatically enters acquisition mode and the falling edge of CS is seen as the first falling
edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC122S706 enters
acquisition mode. While there is no timing restriction with respect to the falling edges of CS and the falling edge
of SCLK, see Figure 6 for setup and hold time requirements for the falling edge of CS with respect to the rising
edge of SCLK.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: ADC122S706