Datasheet

ADC122S706
www.ti.com SNAS408A –NOVEMBER 2007–REVISED MARCH 2013
FUNCTIONAL DESCRIPTION
The ADC122S706 is a dual 12-bit, simultaneous sampling Analog-to-Digital (A/D) converter. The converter is
based on a successive-approximation register (SAR) architecture where the differential nature of the analog
inputs is maintained from the internal track-and-hold circuits throughout the A/D converter. The analog inputs on
both channels are sampled simultaneously to preserve their relative phase information to each other. The
architecture and process allow the ADC122S706 to acquire and convert dual analog signals at sample rates up
to 1 MSPS while consuming very little power.
The ADC122S706 operates from independent analog and digital supplies. The analog supply (V
A
) can range
from 4.5V to 5.5V and the digital supply (V
D
) can range from 2.7V to V
A
. The ADC122S706 utilizes an external
reference. The external reference can be any voltage between 1V and V
A
. The value of the reference voltage
determines the range of the analog input, while the reference input current depends upon the conversion rate.
Analog inputs are presented at the inputs of Channel A and Channel B. Upon initiation of a conversion, the
differential input at these pins is sampled on the internal capacitor array. The inputs are disconnected from the
internal circuitry while a conversion is in progress.
The ADC122S706 requires an external clock. The duty cycle of the clock is essentially unimportant, provided the
minimum clock high and low times are met. The minimum clock frequency is set by internal capacitor leakage.
Each conversion requires 16 SCLK cycles to complete. If less than 12 bits of conversion data are required, CS
can be brought high at any point during the conversion.
The ADC122S706 offers dual high-speed serial data outputs that are binary 2's complement and are compatible
with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces.
Channel A's conversion result is outputted on D
OUTA
while Channel B's conversion result is outputted on D
OUTB
.
This feature makes the ADC122S706 an excellent replacement for systems using two distinct ADCs in a
simultaneous sampling application. The serial clock (SCLK) and chip select bar (CS) are shared by both
channels. The digital conversion of channel A and B is clocked out by the SCLK input and is provided serially,
most significant bit first, at D
OUTA
and D
OUTB
, respectively. The digital data that is provided at D
OUTA
and D
OUTB
is
that of the conversion currently in progress. With CS held low after the conversion is complete, the ADC122S706
continuously converts the analog inputs. For lower power consumption, a single serial data output mode is
externally selectable. This feature makes the ADC122S706 an excellent replacement for two independent ADCs
that are part of a daisy chain configuration.
REFERENCE INPUT
The externally supplied reference voltage sets the analog input range. The ADC122S706 will operate with a
reference voltage in the range of 1V to V
A
.
Operation with a reference voltage below 1V is also possible with slightly diminished performance. As the
reference voltage (V
REF
) is reduced, the range of acceptable analog input voltages is reduced. Assuming a
proper common-mode input voltage, the differential peak-to-peak input range is limited to twice V
REF
. See Input
Common Mode Voltage for more details. Reducing the value of V
REF
also reduces the size of the least significant
bit (LSB). The size of one LSB is equal to twice the reference voltage divided by 4096. When the LSB size goes
below the noise floor of the ADC122S706, the noise will span an increasing number of codes and overall
performance will suffer. For example, dynamic signals will have their SNR degrade, while D.C. measurements
will have their code uncertainty increase. Since the noise is Gaussian in nature, the effects of this noise can be
reduced by averaging the results of a number of consecutive conversions.
Additionally, since offset and gain errors are specified in LSB, any offset and/or gain errors inherent in the A/D
converter will increase in terms of LSB size as the reference voltage is reduced.
The reference input and the analog inputs are connected to the capacitor array through a switch matrix when the
input is sampled. Hence, the current requirements at the reference and at the analog inputs are a series of
transient spikes that occur at a frequency dependent on the operating sample rate of the ADC122S706.
The reference current changes only slightly with temperature. See Figure 38 and Figure 39 in Typical
Performance Characteristics for additional details.
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