Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TSSOP 14

ADC122S706

www.ti.com

SNAS408A –NOVEMBER 2007–REVISED MARCH 2013

ADC122S706 Dual 12-Bit, 500 kSPS to 1 MSPS, Simultaneous Sampling A/D Converter

Check for Samples: ADC122S706

FEATURES

DESCRIPTION

The ADC122S706 is a dual 12-bit, 500 kSPS to 1

• True Simultaneous Sampling Differential

MSPS simultaneous sampling Analog-to-Digital (A/D)

Inputs

converter. The analog inputs on both channels are

• Guaranteed Performance from 500 kSPS to 1

sampled simultaneously to preserve their relative

MSPS

phase information to each other. The converter is

based on a successive-approximation register

• External Reference

architecture where the differential nature of the

• Wide Input Common-Mode Voltage Range

analog inputs is maintained from the internal track-

• Single or Dual High-Speed Serial Data Outputs

and-hold circuits throughout the A/D converter to

• Operating Temperature Range of −40°C to

provide excellent common-mode signal rejection. The

ADC122S706 features an external reference that can

+105°C

be varied from 1.0V to V

• SPI™/QSPI™/MICROWIRE/DSP Compatible

Serial Interface

The ADC122S706 offers dual high-speed serial data

outputs that are binary 2's complement and are

compatible with several standards, such as SPI™,

APPLICATIONS

QSPI™, MICROWIRE, and many common DSP

• Motor Control

serial interfaces. Channel A's conversion result is

• Power Meters/Monitors

outputted on D

OUTA

while Channel B's conversion

result is outputted on D

OUTB

. This feature makes the

• Multi-Axis Positioning Systems

ADC122S706 an excellent replacement for systems

• Instrumentation and Control Systems

using two distinct ADCs in a simultaneous sampling

• Data Acquisition Systems

application. The serial clock (SCLK) and chip select

bar (CS) are shared by both channels. For lower

• Medical Instruments

power consumption, a single serial data output mode

• Direct Sensor Interface

is externally selectable.

The ADC122S706 may be operated with independent

KEY SPECIFICATIONS

analog (V

) and digital (V

) supplies. V

can range

• Conversion Rate: 500 kSPS to 1 MSPS

from 4.5V to 5.5V and V

can range from 2.7V to V

• INL: ±1 LSB (Max)

With the ADC122S706 operating with a V

of 5V and

a V

of 3V, the power consumption at 1 MSPS is

• DNL: ±0.95 LSB (Max)

typically 25 mW. Operating in power-down mode, the

• SNR: 71 dBc (Min)

power consumption of the ADC122S706 decreases to

• THD: -72 dBc (Min)

3 µW. The differential input, low power consumption,

and small size make the ADC122S706 ideal for direct

• ENOB: 11.25 Bits (Min)

connection to sensors in motor control applications.

• Power Consumption at 1 MSPS

Operation is guaranteed over the industrial

– Converting, V

= 5V, V

= 3V: 20 mW (Typ)

temperature range of −40°C to +105°C and clock

– Converting, V

= 5V, V

= 5V: 25 mW (Typ)

rates of 8 MHz to 16 MHz. The ADC122S706 is

– Power-Down: 3 µW (Typ)

available in a 14-lead TSSOP package.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

PAGE 1
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 ADC122S706 Dual 12-Bit, 500 kSPS to 1 MSPS, Simultaneous Sampling A/D Converter Check for Samples: ADC122S706 FEATURES DESCRIPTION • The ADC122S706 is a dual 12-bit, 500 kSPS to 1 MSPS simultaneous sampling Analog-to-Digital (A/D) converter. The analog inputs on both channels are sampled simultaneously to preserve their relative phase information to each other.
PAGE 2
ADC122S706 SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.
PAGE 3
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 PIN DESCRIPTIONS Pin No. Symbol Description 1 VREF Voltage Reference Input. A voltage reference between 1V and VA must be applied to this input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF. A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended for enhanced performance. 2 CHA+ Non-Inverting Input for Channel A.
PAGE 4
ADC122S706 SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) (3) Analog Supply Voltage VA −0.3V to 6.5V Digital Supply Voltage VD −0.3V to (VA +0.3V) max 6.5V −0.3V to (VA +0.
PAGE 5
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 ADC122S706 Converter Electrical Characteristics (1) The following specifications apply for VA = +4.5V to 5.5V, VD = +2.7V to VA, VREF = 2.5V, fSCLK = 8 to 16 MHz, DUAL = VD, fIN = 100 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C.
PAGE 6
ADC122S706 SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com ADC122S706 Converter Electrical Characteristics(1) (continued) The following specifications apply for VA = +4.5V to 5.5V, VD = +2.7V to VA, VREF = 2.5V, fSCLK = 8 to 16 MHz, DUAL = VD, fIN = 100 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C.
PAGE 7
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 ADC122S706 Timing Specifications (1) The following specifications apply for VA = +4.5V to 5.5V, VD = +2.7V to VA, VREF = 2.5V, fSCLK = 8 MHz to 16 MHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits Units 5 11 ns (min) 1/ fSCLK 1/ fSCLK - 3 ns (max) 4 7 ns (min) 1/ fSCLK 1/ fSCLK - 3 ns (max) VD = +2.7V to 3.
PAGE 8
ADC122S706 SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com tACQ tCONV CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK DOUTA DB11 DB10 DB9 4 Leading Zeroes DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Channel A Data tPower Down CS 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCLK DOUTA DB11 DB10 DB9 4 Leading Zeroes DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Channel B Data Figure 2.
PAGE 9
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 Specification Definitions APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is acquired or held for conversion. COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed from 2V to 3V.
PAGE 10
ADC122S706 SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.
PAGE 11
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 Typical Performance Characteristics VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated. DNL - 1 MSPS INL - 1 MSPS Figure 8. Figure 9. DNL vs. VA INL vs. VA Figure 10. Figure 11. DNL vs. VREF INL vs. VREF Figure 12. Figure 13.
PAGE 12
ADC122S706 SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated. 12 DNL vs. SCLK FREQUENCY INL vs. SCLK FREQUENCY Figure 14. Figure 15. DNL vs. TEMPERATURE INL vs. TEMPERATURE Figure 16. Figure 17. SINAD vs. VA THD vs. VA Figure 18. Figure 19.
PAGE 13
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated. SINAD vs. VREF THD vs. VREF Figure 20. Figure 21. SINAD vs. SCLK FREQUENCY THD vs. SCLK FREQUENCY Figure 22. Figure 23. SINAD vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY Figure 24. Figure 25.
PAGE 14
ADC122S706 SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated. 14 SINAD vs. TEMPERATURE THD vs. TEMPERATURE Figure 26. Figure 27. VA CURRENT vs. VA VA CURRENT vs. SCLK FREQ Figure 28. Figure 29. VA CURRENT vs. TEMPERATURE VREF CURRENT vs. SCLK FREQ Figure 30. Figure 31.
PAGE 15
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated. VREF CURRENT vs. TEMP VD CURRENT vs. SCLK FREQ Figure 32. Figure 33. VD CURRENT vs. TEMP VA CURRENT vs. VA (SINGLE DOUT) Figure 34. Figure 35. VA CURRENT vs. SCLK FREQ (SINGLE DOUT) VA CURRENT vs. TEMP (SINGLE DOUT) Figure 36. Figure 37.
PAGE 16
ADC122S706 SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated. 16 VREF CURRENT vs. SCLK (SINGLE DOUT) VREF CURRENT vs. TEMP (SINGLE DOUT) Figure 38. Figure 39. VD CURRENT vs. SCLK (SINGLE DOUT) VD CURRENT vs. TEMP (SINGLE DOUT) Figure 40. Figure 41. CMRR vs. CM RIPPLE FREQ SPECTRAL RESPONSE - 1 MSPS Figure 42.
PAGE 17
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The ADC122S706 is a dual 12-bit, simultaneous sampling Analog-to-Digital (A/D) converter. The converter is based on a successive-approximation register (SAR) architecture where the differential nature of the analog inputs is maintained from the internal track-and-hold circuits throughout the A/D converter.
PAGE 18
ADC122S706 SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com ANALOG SIGNAL INPUTS The ADC122S706 has dual differential inputs where the effective input voltage that is digitized is CHA+ minus CHA− (DIFFINA) and CHB+ minus CHB− (DIFFINB). As is the case with all differential input A/D converters, operation with a fully differential input signal or voltage will provide better performance than with a single-ended input. However, the ADC122S706 can be presented with a single-ended input.
PAGE 19
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 Input Common Mode Voltage The allowable input common mode voltage (VCM) range depends upon the supply and reference voltages used for the ADC122S706. The ranges of VCM are depicted in Figure 46 and Figure 47. Equations for calculating the minimum and maximum common mode voltages for differential and single-ended operation are shown in Table 1.
PAGE 20
ADC122S706 SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com CS Input The CS (chip select bar) is an active low input that is TTL and CMOS compatible. The ADC122S706 is in conversion mode when CS is low and power-down mode when CS is high. As a result, CS frames the conversion window. The falling edge of CS marks the beginning of a conversion and the rising edge of CS marks the end of a conversion window.
PAGE 21
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 Applications Information OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC122S706: −40°C ≤ TA ≤ +105°C +4.5V ≤ VA ≤ +5.5V +2.7V ≤ VD ≤ VA 1V ≤ VREF ≤ VA 8 MHz ≤ fSCLK ≤ 16 MHz VCM: See Input Common Mode Voltage POWER CONSUMPTION The architecture, design, and fabrication process allow the ADC122S706 to operate at conversion rates up to 1 MSPS while consuming very little power.
PAGE 22
ADC122S706 SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com POWER SUPPLY CONSIDERATIONS AND PCB LAYOUT For best performance, care should be taken with the physical layout of the printed circuit board. This is especially true with a low reference voltage or when the conversion rate is high. At high clock rates there is less time for settling, so it is important that any noise settles out before the conversion begins.
PAGE 23
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 APPLICATION CIRCUITS The following figures are examples of the ADC122S706 in typical application circuits. These circuits are basic and will generally require modification for specific circumstances. Data Acquisition Figure 48 shows a basic low cost, low power data acquisition circuit. The analog and digital supply pins are powered by the system +5V supply and the 2.5V reference voltage is generated by the LM4040-2.5 shunt reference.
PAGE 24
ADC122S706 SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Bridge Sensor Application Figure 50 shows an example of interfacing the ADC122S706 to a pair of bridge sensors. The application assumes that the bridge sensors require buffering and amplification to fully utilize the dynamic range of the ADC and thus optimize the performance of the entire signal path. The amplification stage for each ADC input consists of a pair of opamps from the LMP7704.
PAGE 25
ADC122S706 www.ti.com SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013 REVISION HISTORY Changes from Original (March 2013) to Revision A • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 26
PACKAGE OPTION ADDENDUM www.ti.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC122S706CIMTX/NOP B Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 12.
PAGE 28
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device ADC122S706CIMTX/NOP B Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSSOP PW 14 2500 367.0 367.0 35.
PAGE 29
PAGE 30
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.