Datasheet

ADC122S625
www.ti.com SNAS451A –FEBRUARY 2008–REVISED MARCH 2013
ADC122S625 Converter Electrical Characteristics
(1)
(continued)
The following specifications apply for V
A
= +4.5V to 5.5V, V
REF
= 2.5V, f
SCLK
= 1.6 to 6.4 MHz, f
IN
= 20 kHz, C
L
= 25 pF,
unless otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
; all other limits are at T
A
= 25°C.
Symbol Parameter Conditions Typical Limits Units
POWER SUPPLY CHARACTERISTICS
4.5 V (min)
V
A
Analog Supply Voltage
5.5 V (max)
I
VA
Analog Supply Current, f
SCLK
= 6.4 MHz, f
S
= 200 kSPS, f
IN
= 20 kHz,
1.7 2.45 mA (max)
(Conv) Continuously Converting V
A
= 5V
I
VREF
Reference Current, Continuously
f
SCLK
= 6.4 MHz, f
S
= 200 kSPS, V
REF
= 2.5V 20 40 µA (max)
(Conv) Converting
f
SCLK
= 6.4 MHz, V
A
= 5.0V 10 µA
Analog Supply Current, Power Down
I
VA
(PD)
Mode (CS high)
f
SCLK
= 0, V
A
= 5.0V
(2)
0.5 1.1 µA (max)
f
SCLK
= 6.4 MHz, V
REF
= 2.5V 0.05 µA
I
VREF
Reference Current, Power Down
(PD) Mode (CS high)
f
SCLK
= 0, V
REF
= 2.5V
(2)
0.05 0.1 µA (max)
PWR Power Consumption, Continuously f
SCLK
= 6.4 MHz, f
S
= 200 kSPS, f
IN
= 20 kHz,
8.6 12.4 mW (max)
(Conv) Converting V
A
= 5.0V, V
REF
= 2.5V
f
SCLK
= 6.4 MHz, V
A
= 5.0V, V
REF
= 2.5V 50 µW
PWR Power Consumption, Power Down
(PD) Mode (CS high)
f
SCLK
= 0, V
A
= 5.0V, V
REF
= 2.5V 2.6 5.8 µW (max)
See the Specification Definitions for the test
PSRR Power Supply Rejection Ratio −85 dB
condition
AC ELECTRICAL CHARACTERISTICS
f
SCLK
Maximum Clock Frequency 20 6.4 MHz (min)
f
SCLK
Minimum Clock Frequency 0.8 1.6 MHz (max)
Maximum Sample Rate
(3)
625 200 kSPS (min)
f
S
Minimum Sample Rate 25 50 kSPS (min)
t
ACQ
Track/Hold Acquisition Time 3 SCLK cycles
t
CONV
Conversion Time 12 SCLK cycles
t
AD
Aperture Delay 6 ns
(2) Specified by design, characterization, or statistical analysis and is not tested at final test.
(3) While the maximum sample rate is f
SCLK
/32, the actual sample rate may be lower than this by having the CS rate slower than f
SCLK
/32.
ADC122S625 Timing Specifications
(1)
The following specifications apply for V
A
= +4.5V to 5.5V, V
REF
= 2.5V, f
SCLK
= 1.6 MHz to 6.4 MHz, C
L
= 25 pF, unless
otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits Units
4 7 ns (min)
t
CSSU
CS Setup Time prior to an SCLK rising edge
1/ f
SCLK
1/ f
SCLK
- 3 ns (max)
t
EN
D
OUT
Enable Time after the falling edge of CS 9 20 ns (max)
t
DH
D
OUT
Hold time after an SCLK Falling edge 9 6 ns (min)
t
DA
D
OUT
Access time after an SCLK Falling edge 20 26 ns (max)
t
DIS
D
OUT
Disable Time after the rising edge of CS
(2)
10 20 ns (max)
t
CH
SCLK High Time 25 ns (min)
t
CL
SCLK Low Time 25 ns (min)
t
r
D
OUT
Rise Time 7 ns
t
f
D
OUT
Fall Time 7 ns
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) t
DIS
is the time for D
OUT
to change 10%.
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