Datasheet
SAR
SERIAL
INTERFACE
COMPARATOR
S/H
CHARGE
REDISTRIBUTION
DAC
CHA+
CHA-
V
REF
SAR
COMPARATOR
S/H
CHARGE
REDISTRIBUTION
DAC
CHB-
CHB+
ADC122S625
SNAS451A –FEBRUARY 2008–REVISED MARCH 2013
www.ti.com
Block Diagram
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin No. Symbol Description
Voltage Reference Input. A voltage reference between 1V and V
A
must be applied to this
input. V
REF
must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF.
1 V
REF
A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended for
enhanced performance.
Non-Inverting Input for Channel A. CHA+ is the positive analog input for the differential
2 CHA+
signal applied to Channel A.
Inverting Input for Channel A. CHA− is the negative analog input for the differential signal
3 CHA−
applied to Channel A.
Inverting Input for Channel B. CHB− is the negative analog input for the differential signal
4 CHB−
applied to Channel B.
Non-Inverting Input for Channel B. CHB+ is the positive analog input for the differential
5 CHB+
signal applied to Channel B.
6 GND Ground. GND is the ground reference point for all signals applied to the ADC122S625.
Analog Power Supply input. A voltage source between 4.5V and 5.5V must be applied to
this input. V
A
must be decoupled to GND with a minimum ceramic capacitor value of 0.1
7 V
A
µF. A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended for
enhanced performance.
Serial Data Output for Channel A and Channel B. The serial data output word is comprised
of 4 null bits, 12 data bits (ChA conversion result), 4 null bits, and 12 data bits (ChB
8 D
OUT
conversion result). During a conversion, the data is output on the falling edges of SCLK and
is valid on the rising edges.
9 SCLK Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.
Chip Select Bar. CS is active low. The ADC122S625 is actively converting when CS is
10 CS
LOW and Power-Down Mode when CS is HIGH. A conversion begins on the fall of CS.
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