Datasheet

ADC122S625
SNAS451A –FEBRUARY 2008–REVISED MARCH 2013 www.ti.com
Table 2. Ideal Output Code vs. Input Voltage
Analog Input
2's Complement Binary Output 2's Comp. Hex Code 2's Comp. Dec Code
(+IN) − (−IN)
V
REF
− 1.5 LSB 0111 1111 1111 7FF 2047
+ 0.5 LSB 0000 0000 0001 001 1
− 0.5 LSB 0000 0000 0000 000 0
0V − 1.5 LSB 1111 1111 1111 FFF −1
−V
REF
+ 0.5 LSB 1000 0000 0000 800 −2048
While data is output on the falling edges of SCLK, receiving systems have the option of capturing the data from
the ADC122S625 on the subsequent rising or falling edge of SCLK. If a receiving system is going to capture data
on the subsequent falling edges of SCLK, it is important to make sure that the minimum hold time after an SCLK
falling edge (t
DH
) is acceptable. See Figure 4 for D
OUT
hold and access times.
D
OUT
is enabled on the falling edge of CS and disabled on the rising edge of CS. If CS is raised prior to the 16th
falling edge of SCLK, the current conversion is aborted and D
OUT
will go into its high impedance state. A new
conversion will begin when CS is taken LOW.
Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC122S625:
−40°C ≤ T
A
≤ +105°C
+4.5V ≤ V
A
≤ +5.5V
1V ≤ V
REF
≤ V
A
1.6 MHz ≤ f
SCLK
≤ 6.4 MHz
V
CM
: See Input Common Mode Voltage
POWER CONSUMPTION
The architecture, design, and fabrication process allow the ADC122S625 to operate at conversion rates up to
200 kSPS while consuming very little power. The ADC122S625 consumes the least amount of power while
operating in power down mode. For applications where power consumption is critical, the ADC122S625 should
be operated in power down mode as often as the application will tolerate. To further reduce power consumption,
stop the SCLK while CS is high.
Burst Mode Operation
Normal operation of the ADC122S625 requires the SCLK frequency to be thirty-two times the sample rate and
the CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications
requiring sample rates below 50 kSPS, the ADC122S625 should be run with an SCLK frequency of 6.4 MHz and
a CS rate as slow as the system requires. When this is accomplished, the ADC122S625 is operating in burst
mode. The ADC122S625 enters into power down mode at the end of each conversion, minimizing power
consumption. This causes the converter to spend the longest possible time in power down mode. Since power
consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest
conversion rate that will satisfy the requirements of the system.
POWER SUPPLY CONSIDERATIONS AND PCB LAYOUT
For best performance, care should be taken with the physical layout of the printed circuit board. This is especially
true with a low reference voltage or when the conversion rate is high. At high clock rates there is less time for
settling, so it is important that any noise settles out before the conversion begins.
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