Datasheet

ADC122S625
www.ti.com SNAS451A –FEBRUARY 2008–REVISED MARCH 2013
During the first three cycles of SCLK, the ADC122S625 is in acquisition mode (t
ACQ
), tracking the input voltage
on both Channel A and Channel B. For the next twelve SCLK cycles (t
CONV
), the conversion of Channel A and
Channel B is accomplished simultaneously and data is presented on D
OUT
, one bit at a time. SCLK falling edges
one through four clock out leading zeros while falling edges five through sixteen clock out the conversion result
of Channel A, MSB first. The process is repeated in order to clock out the result of Channel B, with SCLK falling
edges seventeen through twenty clocking out four zeros followed by falling edges twenty-one through thirty-two
clokcing out the conversion result of Channel B. If there is more than one conversion in a frame (continuous
conversion mode), the ADC122S625 will re-enter acquisition mode on the falling edge of SCLK after the N*32
rising edge of SCLK and re-enter conversion mode on the N*32+4 falling edge of SCLK as shown in Figure 2.
"N" is an integer value.
The ADC122S625 can enter acquisition mode under three different conditions. The first condition involves CS
going low (asserted) with SCLK high. In this case, the ADC122S625 enters acquisition mode on the first falling
edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this condition,
the ADC122S625 automatically enters acquisition mode and the falling edge of CS is seen as the first falling
edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC122S625 immediately
enters acquisition mode. While there is no timing restriction with respect to the falling edges of CS and the falling
edge of SCLK, see Figure 5 for setup and hold time requirements for the falling edge of CS with respect to the
rising edge of SCLK.
CS Input
The CS (chip select bar) is an active low input that is TTL and CMOS compatible. The ADC122S625 transitions
from acquisition mode, to conversion mode, to power-down mode when CS is low and is always in power-down
mode when CS is high. The falling edge of CS marks the beginning of a conversion where the input to Channel
A and Channel B are tracked by the input sampling capacitor. The rising edge of CS marks the end of a
conversion window. As a result, CS frames the conversion window and can be used to control the sample rate of
the ADC122S625. While the SCLK frequency is limited to a range of 1.6 MHz to 6.4 MHz, the frequency of CS
has no limitation. This allows a system designer to operate the ADC122S625 at sample rates approaching zero
samples per second if conserving power is very important. See Burst Mode Operation for more details. Multiple
conversions can occur within a given conversion frame with each conversion requiring thirty-two SCLK cycles.
This is referred to as continuous conversion mode and is shown in Figure 2 of the Timing Diagrams section.
Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS
occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is
clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature,
and characteristics of the individual device. To ensure that the MSB is always clocked out at a given time (the
5th falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in the
Timing Specification table.
SCLK Input
The SCLK (serial clock) serves two purposes in the ADC122S625. It is used by the ADC122S625 as the
conversion clock and it is used as the serial clock to output the conversion results. The SCLK input is TTL and
CMOS compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor
leakage limits the minimum clock frequency. The ADC122S625 offers specified performance with the clock rates
indicated in the Electrical Characteristics Table.
Data Output(s)
The conversion result of Channel A and Channel B is output on D
OUT
, with the result of Channel A being output
before the result of Channel B. The data output format of the ADC122S625 is binary, two’s complement, as
shown in Table 2. This table indicates the ideal output code for a given input voltage and does not include the
effects of offset, gain error, linearity errors, or noise. Each data output bit is output on the falling edges of SCLK.
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