Datasheet

Single-Ended Input
1.25
0.0 0.75 1.75 2.5
3.75
V
A
= 5.0V
V
REF
(V)
COMMON-MODE VOLTAGE (V)
2.5
0
5
-1
6
1.25
Differential Input
1.25
0.0 1.0 2.0 3.0 4.0 5.0
3.75
V
A
= 5.0V
V
REF
(V)
COMMON-MODE VOLTAGE (V)
2.5
0
5
-1
6
2.5
ADC122S625
SNAS451A –FEBRUARY 2008–REVISED MARCH 2013 www.ti.com
Input Common Mode Voltage
The allowable input common mode voltage (V
CM
) range depends upon the supply and reference voltages used
for the ADC122S625. The ranges of V
CM
for differential and single-ended operation are depicted in Figure 36 and
Figure 37. Equations for calculating the minimum and maximum common mode voltages for differential and
single-ended operation are shown in Table 1.
Figure 36. V
CM
range for Differential Input operation
Figure 37. V
CM
range for single-ended operation
Table 1. Allowable V
CM
Range
Input Signal Minimum V
CM
Maximum V
CM
Differential V
REF
/ 2 V
A
− V
REF
/ 2
Single-Ended V
REF
V
A
− V
REF
SERIAL DIGITAL INTERFACE
The ADC122S625 communicates via a synchronous serial interface as shown in the Timing Diagrams section.
CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the
conversion process and the timing of the serial data. D
OUT
is the serial data output pin, where the conversion
results of Channel A and Channel B are sent as a serial data stream, with the result of Channel A output before
the result of Channel B.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC122S625's D
OUT
is in a high impedance state when CS is high (asserted) and is active when CS is low (de-asserted); thus CS
acts as an output enable. A timing diagram for a single conversion is shown in Figure 1.
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