Datasheet
ADC122S021
www.ti.com
SNAS280D –MARCH 2005–REVISED MARCH 2013
ADC122S021 CONVERTER ELECTRICAL CHARACTERISTICS
(1)
(continued)
The following specifications apply for V
A
= +2.7V to 5.25V, GND = 0V, f
SCLK
= 0.8 MHz to 3.2 MHz, f
SAMPLE
= 50 ksps to 200
ksps, C
L
= 35 pF unless otherwise noted. Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits
(2)
Units
C
OUT
TRI-STATE® Output Capacitance 2 4 pF (max)
Output Coding Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (C
L
= 10 pF)
2.7 V (min)
V
A
Analog Supply Voltage
5.25 V (max)
V
A
= +5.25V,
1.5 2.1 mA (max)
f
SAMPLE
= 200 ksps, f
IN
= 39.9 kHz
Supply Current, Normal Mode
(Operational, CS low)
V
A
= +3.6V,
0.62 1.0 mA (max)
f
SAMPLE
= 200 ksps, f
IN
= 39.9 kHz
I
A
V
A
= +5.25V,
60 nA
f
SAMPLE
= 0 ksps
Supply Current, Shutdown (CS high)
V
A
= +3.6V,
38 nA
f
SAMPLE
= 0 ksps
V
A
= +5.25V 7.9 11 mW (max)
Power Consumption, Normal Mode
(Operational, CS low)
V
A
= +3.6V 2.2 3.6 mW (max)
P
D
V
A
= +5.25V 0.32 µW
Power Consumption, Shutdown (CS
high)
V
A
= +3.6V 0.14 µW
AC ELECTRICAL CHARACTERISTICS
0.8 MHz (min)
f
SCLK
Maximum Clock Frequency
(3)
3.2 MHz (max)
50 ksps (min)
f
S
Sample Rate
(3)
200 ksps (max)
t
CONV
Conversion Time 13 SCLK cycles
30 % (min)
DC SCLK Duty Cycle f
SCLK
= 3.2 MHz 50
70 % (max)
t
ACQ
Track/Hold Acquisition Time Full-Scale Step Input 3 SCLK cycles
Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles
(3) This is the frequency range over which the electrical performance is specified. The device is functional over a wider range which is
specified under Operating Ratings.
ADC122S021 TIMING SPECIFICATIONS
The following specifications apply for V
A
= +2.7V to 5.25V, GND = 0V, f
SCLK
= 0.8 MHz to 3.2 MHz, f
SAMPLE
= 50 ksps to 200
ksps, C
L
= 35 pF, Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits
(1)
Units
V
A
= +3.0V −3.5
t
CSU
Setup Time SCLK High to CS Falling Edge
(2)
10 ns (min)
V
A
= +5.0V −0.5
V
A
= +3.0V +4.5
t
CLH
Hold time SCLK Low to CS Falling Edge
(2)
10 ns (min)
V
A
= +5.0V +1.5
V
A
= +3.0V +4
t
EN
Delay from CS Until DOUT active 30 ns (max)
V
A
= +5.0V +2
V
A
= +3.0V +14.5
t
ACC
Data Access Time after SCLK Falling Edge 30 ns (max)
V
A
= +5.0V +13
t
SU
Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min)
t
H
Data Valid SCLK Hold Time +3 10 ns (min)
0.3 x
t
CH
SCLK High Pulse Width 0.5 x t
SCLK
ns (min)
t
SCLK
(1) Tested limits are ensured to Texas Instruments' AOQL (Average Outgoing Quality Level).
(2) Clock may be either high or low when CS is asserted as long as setup and hold times t
CSU
and t
CLH
are strictly observed..
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