Datasheet

SCL
SDA
START
1 2 6 7
8
9
8-ELW0DVWHUFRGH³00001[[[´
Not-Acknowledge
from the Device
NACK
5
Standard-Fast Mode Hs-Mode
Repeated
START
1 2
MSB
7-bit Slave
Address
ADC121C021, ADC121C021Q, ADC121C027
www.ti.com SNAS415F –JANUARY 2008–REVISED MARCH 2013
Figure 26. Beginning Hs-Mode Communication
I
2
C Slave (Hardware) Address
The ADC has a seven-bit hardware address which is also referred to as a slave address. For the VSSOP version
of the ADC121C021, this address is configured by the ADR0 and ADR1 addres selection inputs. For the
ADC121C027, the address is configured by the ADR0 address selection input. ADR0 and ADR1 can be
grounded, left floating, or tied to V
A
. If desired, ADR0 and ADR1 can be set to V
A
/2 rather than left floating. The
state of these inputs sets the hardware address that the ADC responds to on the I
2
C bus (see Table 1). For the
ADC121C021, the hardware address is not pin-configurable and is set to 1010100. The diagrams in
Communicating with the ADC121C021 describes how the I
2
C controller should address the ADC via the I
2
C
interface.
Table 1. Slave Addresses
ADC121C027 ADC121C021 ADC121C021
Slave Address
(SOT) (SOT) (VSSOP)
[A6 - A0]
ADR0 ALERT ADR1 ADR0
1010000 Floating ----------------- Floating Floating
1010001 GND ----------------- Floating GND
1010010 V
A
----------------- Floating V
A
1010100 ----------------- Single Address GND Floating
1010101 ----------------- ----------------- GND GND
1010110 ----------------- ----------------- GND V
A
1011000 ----------------- ----------------- V
A
Floating
1011001 ----------------- ----------------- V
A
GND
1011010 ----------------- ----------------- V
A
V
A
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Product Folder Links: ADC121C021 ADC121C021Q ADC121C027