Datasheet

ADC121C021, ADC121C021Q, ADC121C027
www.ti.com SNAS415F –JANUARY 2008–REVISED MARCH 2013
V
HIGH
-- Alert Limit Register - Over Range
This register holds the upper limit threshold used to determine the alert condition. If the conversion moves higher
than this limit, a V
HIGH
alert is generated.
Pointer Address 04h (Read/Write)
Default Value: 0FFFh
D15 D14 D13 D12 D11 D10 D9 D8
Reserved V
HIGH
Limit [11:8]
D7 D6 D5 D4 D3 D2 D1 D0
V
HIGH
Limit [7:0]
Bits Name Description
15:12 Reserved Always reads zeros. Zeros must be written to these bits.
11:0 V
HIGH
Limit Upper limit threshold. D11 is MSB.
V
HYST
-- Alert Hysteresis Register
This register holds the hysteresis value used to determine the alert condition. After a V
HIGH
or V
LOW
alert occurs,
the conversion result must move within the V
HIGH
or V
LOW
limit by more than this value to clear the alert
condition. Note: If the Alert Hold bit is set in the configuration register, alert conditions will not self-clear.
Pointer Address 05h (Read/Write)
Default Value: 0000h
D15 D14 D13 D12 D11 D10 D9 D8
Reserved Hysteresis [11:8]
D7 D6 D5 D4 D3 D2 D1 D0
Hysteresis [7:0]
Bits Name Description
15:12 Reserved Always reads zeros. Zeros must be written to these bits.
11:0 Hysteresis Hysteresis value. D11 is MSB.
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