Datasheet

1 9
ACK
by
ADC
Start by
Master
R/W
ACK
by
Master
Frame 1
Address Byte
from Master
D7 D6 D5 D4 D3 D2 D1 D0
1 9
NACK
by
Master
Stop
by
Master
1 9
D15 D14 D13 D12 D11 D10 D9 D8
ACK
by
Master
Frame 4
Upper Data Byte
from ADC
Frame 5
Lower Data Byte
from ADC
Repeat Frames
4 and 5 for
Continuous Mode
A2 A0A1A3A4A5A6
SCL
SDA
SCL
(continued)
SDA
(continued)
D7 D6 D5 D4 D3 D2 D1 D0
1 9
1 9
D15 D14 D13 D12 D11 D10 D9 D8
ACK
by
Master
Frame 2
Upper Data Byte
from ADC
Frame 3
Lower Data Byte
from ADC
Interface Delay
t
Quiet
8 1us
Interface Delay
t
Quiet
8 1us
ADC121C021, ADC121C021Q, ADC121C027
SNAS415F –JANUARY 2008–REVISED MARCH 2013 www.ti.com
QUIET INTERFACE MODE
To improve performance at High Speed, operate the ADC in Quiet Interface Mode. This mode provides improved
INL and DNL performance in I
2
C Hs-Mode (3.4MHz). The Quiet Interface mode provides a maximum throughput
rate of 162ksps. Figure 35 describes how to read the conversion result register in this mode. Basically, the
Master needs to release SCL for at least 1µs before the MSB of every upper data byte. The diagram assumes
that the address pointer register is set to its default value.
Quiet Interface mode will only improve INL and DNL performance in Hs-Mode. Standard and Fast mode
performance is unaffected by the Quiet Interface mode.
Figure 35. Reading in Quiet Interface Mode
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