Datasheet
ADC121C021, ADC121C021Q, ADC121C027
SNAS415F –JANUARY 2008–REVISED MARCH 2013
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Bits Name Description
7:5 Cycle Time Configures Automatic Conversion mode. When these bits are set to zeros, the automatic conversion
mode is disabled. This is the case at power-up.
When these bits are set to a non-zero value, the ADC will begin operating in automatic conversion
mode (see Automatic Conversion Mode). The Cycle Time table shows how different values provide
various conversion intervals.
4 Alert Hold 0: Alerts will self-clear when the measured voltage moves within the limits by more than the hysteresis
register value.
1: Alerts will not self-clear and are only cleared when a one is written to the alert high flag or the alert
low flag in the Alert Status register.
3 Alert Flag Enable 0: Disables alert status bit [D15] in the Conversion Result register.
1: Enables alert status bit [D15] in the Conversion Result register.
2 Alert Pin Enable 0: Disables the ALERT output pin. The ALERT output will be high impedance when the pin is disabled.
1: Enables the ALERT output pin.
*This bit does not apply to and is a "don't care" for the ADC121C027.
1 Reserved Always reads zeros. Zeros must be written to this bit.
0 Polarity This bit configures the active level polarity of the ALERT output pin.
0: Sets the ALERT pin to active low.
1: Sets the ALERT pin to active high.
*This bit does not apply to and is a "don't care" for the ADC121C027.
V
LOW
-- Alert Limit Register - Under Range
This register holds the lower limit threshold used to determine the alert condition. If the conversion moves lower
than this limit, a V
LOW
alert is generated.
Pointer Address 03h (Read/Write)
Default Value: 0000h
D15 D14 D13 D12 D11 D10 D9 D8
Reserved V
LOW
Limit [11:8]
D7 D6 D5 D4 D3 D2 D1 D0
V
LOW
Limit [7:0]
Bits Name Description
15:12 Reserved Always reads zeros. Zeros must be written to these bits.
11:0 V
LOW
Limit Lower limit threshold. D11 is MSB.
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