Datasheet

ADC12130, ADC12132, ADC12138
www.ti.com SNAS098G –MARCH 2000–REVISED MARCH 2013
DC and Logic Electrical Characteristics (continued)
The following specifications apply for (V
+
= V
A
+ = V
D
+ = +5V, V
REF
+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+
= V
A
+ = V
D
+ = +3.3V, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), V
REF
− = 0V, 12-bit + sign conversion mode
(1)
, source impedance for analog inputs, V
REF
− and V
REF
+ ≤ 25Ω,
f
CK
= f
SK
= 5 MHz, and 10 (t
CK
) acquisition time unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25°C.
(2)(3)(4)
V
+
= V
A
+ = V
+
= V
A
+ =
Typical Units
Parameter Test Conditions V
D
+ = 3.3V V
D
+ = 5V
(5)
(Limits)
Limits
(6)
Limits
(6)
POWER SUPPLY CHARACTERISTICS
Awake (Active) 1.5 2.5 mA (max)
CS = HIGH, Powered Down,
600 μA
I
D
+ Digital Supply Current CCLK on
CS = HIGH, Powered Down,
20 μA
CCLK off
Awake (Active) 3.0 4.0 mA (max)
CS = HIGH, Powered Down, 10
μA
I
A
+ Positive Analog Supply Current CCLK on
CS = HIGH, Powered Down, 0.1
μA
CCLK off
CS = HIGH, Powered Down,
70 μA
CCLK on
I
REF
Reference Input Current
CS = HIGH, Powered Down,
0.1 μA
CCLK off
AC Electrical Characteristics
The following specifications apply for (V
+
= V
A
+ = V
D
+ = +5V, V
REF
+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+
= V
A
+ = V
D
+ = +3.3V, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), V
REF
− = 0V, 12-bit + sign conversion mode
(1)
, source impedance for analog inputs, V
REF
− and V
REF
+ ≤ 25Ω,
f
CK
= f
SK
= 5 MHz, and 10 (t
CK
) acquisition time unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25°C.
(2)
Parameter Test Conditions Typical
(3)
Limits
(4)
Units (Limits)
10 5 MHz (max)
f
CK
Conversion Clock (CCLK) Frequency
1 MHz (min)
10 5 MHz (max)
f
SK
Serial Data Clock SCLK Frequency
0 Hz (min)
40 % (min)
Conversion Clock Duty Cycle
60 % (max)
40 % (min)
Serial Data Clock Duty Cycle
60 % (max)
44(t
CK
) 44(t
CK
) (max)
t
C
Conversion Time 12-Bit + Sign or 12-Bit
8.8 μs (max)
(1) The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device.
Therefore, the output data from these modes are not an indication of the accuracy of a conversion result.
(2) Timing specifications are tested at the TTL logic levels, V
OL
= 0.4V for a falling edge and V
OL
= 2.4V for a rising edge. TRI-STATE
output voltage is forced to 1.4V.
(3) Typical figures are at T
J
= T
A
= 25°C and represent most likely parametric norm.
(4) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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