Datasheet
ADC12130, ADC12132, ADC12138
SNAS098G –MARCH 2000–REVISED MARCH 2013
www.ti.com
Converter Electrical Characteristics (continued)
The following specifications apply for (V
+
= V
A
+ = V
D
+ = +5V, V
REF
+ = +4.096V, and fully differential input with fixed 2.048V
common-mode voltage) or (V
+
= V
A
+ = V
D
+ = 3.3V, V
REF
+ = 2.5V and fully-differential input with fixed 1.250V common-mode
voltage), V
REF
− = 0V, 12-bit + sign conversion mode
(1)
, source impedance for analog inputs, V
REF
−
and V
REF
+
≤ 25Ω, f
CK
= f
SK
= 5 MHz, and 10 (t
CK
) acquisition time unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other
limits T
A
= T
J
= 25°C.
(2)(3)(4)
Units
Parameter Test Conditions Typical
(5)
Limits
(6)
(Limits)
Channel-to-Channel Crosstalk V
IN
= 5 V
PP
, f
IN
= 40 kHz −72 dB
MUX Bandwidth 90 kHz
DC and Logic Electrical Characteristics
The following specifications apply for (V
+
= V
A
+ = V
D
+ = +5V, V
REF
+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+
= V
A
+ = V
D
+ = +3.3V, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), V
REF
− = 0V, 12-bit + sign conversion mode
(1)
, source impedance for analog inputs, V
REF
− and V
REF
+ ≤ 25Ω,
f
CK
= f
SK
= 5 MHz, and 10 (t
CK
) acquisition time unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25°C.
(2)(3)(4)
V
+
= V
A
+ = V
+
= V
A
+ =
Typical Units
Parameter Test Conditions V
D
+ = 3.3V V
D
+ = 5V
(5)
(Limits)
Limits
(6)
Limits
(6)
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
V
IN(1)
Logical “1” Input Voltage V
A
+ = V
D
+ = V
+
+10% 2.0 2.0 V (min)
V
IN(0)
Logical “0” Input Voltage V
A
+ = V
D
+ = V
+
−10% 0.8 0.8 V (max)
I
IN(1)
Logical “1” Input Current V
IN
= V
+
0.005 1.0 1.0 μA (max)
I
IN(0)
Logical `“0” Input Current V
IN
= 0V −0.005 −1.0 −1.0 μA (min)
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
V
A
+ = V
D
+ = V
+
− 10%,
2.4 2.4 V (min)
I
OUT
= −360 μA
V
OUT(1)
Logical “1” Output Voltage
V
A
+ = V
D
+ = V
+
− 10%,
2.9 4.25 V (min)
I
OUT
= −10 μA
V
A
+ = V
D
+ = V
+
− 10%
V
OUT(0)
Logical “0” Output Voltage 0.4 0.4 V (max)
I
OUT
= 1.6 mA
V
OUT
= 0V −0.1 −3.0 −3.0 μA (max)
I
OUT
TRI-STATE Output Current
V
OUT
= V
+
−0.1 3.0 3.0 μA (max)
+I
SC
Output Short Circuit Source Current V
OUT
= 0V −14 mA
−I
SC
Output Short Circuit Sink Current V
OUT
= V
D
+ 16 mA
(1) The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device.
Therefore, the output data from these modes are not an indication of the accuracy of a conversion result.
(2) Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above V
A
+
or 5V below GND will not damage this device. However, errors in conversion can occur (if these diodes are forward biased by more than
50 mV) if the input voltage magnitude of selected or unselected analog input go above V
A
+ or below GND by more than 50 mV. As an
example, if V
A
+ is 4.5 V
DC
, full-scale input voltage must be ≤4.55 V
DC
to ensure accurate conversions.
(3) To ensure accuracy, it is required that the V
A
+ and V
D
+ be connected together to the same power supply with separate bypass
capacitors at each V
+
pin.
(4) With the test condition for V
REF
(V
REF
+ − V
REF
−) given as +4.096V, the 12-bit LSB is 1.0 mV. For V
REF
= 2.5V, the 12-bit LSB is 610 μV.
(5) Typical figures are at T
J
= T
A
= 25°C and represent most likely parametric norm.
(6) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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