Datasheet

ADC12130, ADC12132, ADC12138
SNAS098G –MARCH 2000–REVISED MARCH 2013 www.ti.com
10.0 GROUNDING
The ADC12130/2/8's performance can be maximized through proper grounding techniques. These include the
use of separate analog and digital areas of the board with analog and digital components and traces located only
in their respective areas. Bypass capacitors of 0.01 µF and 0.1 µF surface mount capacitors and a 10 µF are
recommended at each of the power supply pins for best performance. These capacitors should be located as
close to the bypassed pin as practical, especially the smaller value capacitors.
11.0 CLOCK SIGNAL LINE ISOLATION
The ADC12130/2/8's performance is optimized by routing the analog input/output and reference signal
conductors as far as possible from the conductors that carry the clock signals to the CCLK and SCLK pins.
Maintaining a separation of at least 7 to 10 times the height of the clock trace above its reference plane is
recommended.
12.0 THE CALIBRATION CYCLE
A calibration cycle needs to be started after the power supplies, reference, and clock have been given enough
time to stabilize after initial turn-on. During the calibration cycle, correction values are determined for the offset
voltage of the sampled data comparator and any linearity and gain errors. These values are stored in internal
RAM and used during an analog-to-digital conversion to bring the overall full-scale, offset, and linearity errors
down to the specified limits. Full-scale error typically changes ±0.4 LSB over temperature and linearity error
changes even less; therefore, it should be necessary to go through the calibration cycle only once after power up
if the Power Supply Voltage and the ambient temperature do not change significantly (see the curves in the
Typical Performance Characteristics).
13.0 THE Auto Zero CYCLE
To correct for any change in the zero (offset) error of the ADC, the Auto Zero cycle can be used. It may be
desirable to do an Auto Zero cycle whenever the ambient temperature or the power supply voltage change
significantly. (See the curves, Figure 17 and Figure 19, in the Typical Performance Characteristics.)
14.0 DYNAMIC PERFORMANCE
Many applications require the converter to digitize AC signals, but the standard DC integral and differential
nonlinearity specifications will not accurately predict the converter's performance with AC input signals. The
important specifications for AC applications reflect the converter's ability to digitize AC signals without significant
spectral errors and without adding noise to the digitized signal. Dynamic characteristics such as signal-to-noise
(S/N), signal-to-noise + distortion ratio or S/(N + D), effective bits, full power bandwidth, aperture time and
aperture jitter are quantitative measures of the converter's capability.
An ADC's AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal
waveform is applied to the ADC's input, and the transform is then performed on the digitized waveform. S/(N + D)
and S/N are calculated from the resulting FFT data, and a spectral plot may also be obtained. Typical values for
S/N are shown in Converter Electrical Characteristics, and spectral plots of S/(N + D) are included in Typical
Performance Characteristics.
The ADC's noise and distortion levels will change with the frequency of the input signal, with more distortion and
noise occurring at higher signal frequencies. This can be seen in the S/(N + D) versus frequency curves. These
curves will also give an indication of the full power bandwidth (the frequency at which the S/(N + D) or S/N drops
3 dB).
Effective number of bits can also be useful in describing the ADC's noise and distortion performance. An ideal
ADC will have some amount of quantization noise, determined by its resolution, and no distortion, which will yield
an optimum S/(N + D) ratio given by the following equation:
S/(N + D) = (6.02 × n + 1.76) dB
where
• "n" is the ADC's resolution in bits (2)
The effective bits of an actual ADC can be found by:
n(effective) = ENOB = (S/(N + D) - 1.76) / 6.02 (3)
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