Datasheet

ADC12130, ADC12132, ADC12138
SNAS098G –MARCH 2000–REVISED MARCH 2013 www.ti.com
1.3 CS Low Continuously Considerations
When CS is continuously low, it is important to transmit the exact number of SCLK pulses that the ADC expects.
Not doing so will desynchronize the serial communications to the ADC. When the supply power is first applied to
the ADC, it will expect to see 13 SCLK pulses for each I/O transmission. The number of SCLK pulses that the
ADC expects to see is the same as the digital output word length. The digital output word length is controlled by
the Data Out (DO) format. The DO format maybe changed any time a conversion is started or when the sign bit
is turned on or off. The table below details out the number of clock periods required for different DO formats:
DO Format Number of SCLKs Expected
SIGN OFF 12
12-Bit MSB or LSB First
SIGN ON 13
SIGN OFF 16
16-Bit MSB or LSB first
SIGN ON 17
If erroneous SCLK pulses desynchronize the communications, the simplest way to recover is by cycling the
power supply to the device. Not being able to easily resynchronize the device is a shortcoming of leaving CS low
continuously.
The number of clock pulses required for an I/O exchange may be different for the case when CS is left low
continuously vs. the case when CS is cycled. Take the I/O sequence detailed in Figure 65 as an example. The
table below lists the number of SCLK pulses required for each instruction:
Instruction CS Low Continuously CS Strobed
Auto Cal 13 SCLKs 8 SCLKs
Read Status 13 SCLKs 8 SCLKs
Read Status 13 SCLKs 8 SCLKs
12-Bit + Sign Conv 1 13 SCLKs 8 SCLKs
12-Bit + Sign Conv 2 13 SCLKs 13 SCLKs
1.4 Analog Input Channel Selection
The data input at DI also selects the channel configuration (see Table 2, Table 3, and Table 4). In Figure 66 the
only times when the channel configuration could be modified would be during I/O sequences 1, 4, 5 and 6. Input
channels are reselected before the start of each new conversion. Shown below is the data bit stream required at
DI during I/O sequence number 4 in Figure 66 to set CH1 as the positive input and CH0 as the negative input for
the different ADC versions.
Part DI Data
(1)
Number
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
ADC12130andADC12132 L H L L H L X X
ADC12138 L H L L L L H L
(1) X can be a logic high (H) or low (L).
1.5 Power Up/Down
The ADC may be powered down by taking the PD pin HIGH or by the instruction input at DI (see Table 4,
Table 5, Figure 59, Figure 60, and Figure 61). When the ADC is powered down in this way, the ADC conversion
circuitry is deactivated but the digital I/O circuitry is kept active.
Hardware power up/down is controlled by the state of the PD pin. Software power-up/down is controlled by the
instruction issued to the ADC. If a software power up instruction is issued to the ADC while a hardware power
down is in effect (PD pin high) the device will remain in the power-down state. If a software power down
instruction is issued to the ADC while a hardware power up is in effect (PD pin low), the device will power down.
When the device is powered down by software, it may be powered up by either issuing a software power up
instruction or by taking PD pin high and then low. If the power down command is issued during a conversion, that
conversion is interrupted, so the data output after power up cannot be relied upon.
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