Datasheet

ADC12130, ADC12132, ADC12138
www.ti.com SNAS098G –MARCH 2000–REVISED MARCH 2013
AC Electrical Characteristics (continued)
The following specifications apply for (V
+
= V
A
+ = V
D
+ = +5V, V
REF
+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+
= V
A
+ = V
D
+ = +3.3V, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), V
REF
− = 0V, 12-bit + sign conversion mode
(1)
, source impedance for analog inputs, V
REF
− and V
REF
+ ≤ 25Ω,
f
CK
= f
SK
= 5 MHz, and 10 (t
CK
) acquisition time unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25°C.
(2)
(Continued)
Units
Parameter Test Conditions Typical
(3)
Limits
(4)
(Limits)
Hardware Power-Up Time, Time from PD
t
HPU
500 700 μs (max)
Falling Edge to EOC Rising Edge
Software Power-Up Time, Time from Serial
t
SPU
500 700 μs (max)
Data Clock Falling Edge to EOC Rising Edge
Access Time Delay from CS Falling Edge to
t
ACC
25 60 ns (max)
DO Data Valid
Set-Up Time of CS Falling Edge to Serial Data
t
SET-UP
50 ns (min)
Clock Rising Edge
Delay from SCLK Falling Edge to CS Falling
t
DELAY
0 5 ns (min)
Edge
t
1H
, t
0H
Delay from CS Rising Edge to DO TRI-STATE R
L
= 3k, C
L
= 100 pF 70 100 ns (max)
DI Hold Time from Serial Data Clock Rising
t
HDI
5 15 ns (max)
Edge
DI Set-Up Time from Serial Data Clock Rising
t
SDI
5 10 ns (min)
Edge
DO Hold Time from Serial Data Clock Falling 35 65 ns (max)
t
HDO
R
L
= 3k, C
L
= 100 pF
Edge 5 ns (min)
Delay from Serial Data Clock Falling Edge to
t
DDO
50 90 ns (max)
DO Data Valid
DO Rise Time, TRI-STATE to High DO Rise 10 40 ns (max)
t
RDO
R
L
= 3k, C
L
= 100 pF
Time, Low to High 10 40 ns (max)
DO Fall Time, TRI-STATE to Low DO Fall 15 40 ns (max)
t
FDO
R
L
= 3k, C
L
= 100 pF
Time, High to Low 15 40 ns (max)
Delay from CS Falling Edge to DOR Falling
t
CD
45 80 ns (max)
Edge
Delay from Serial Data Clock Falling Edge to
t
SD
45 80 ns (max)
DOR Rising Edge
C
IN
Capacitance of Logic Inputs 20 pF
C
OUT
Capacitance of Logic Outputs 20 pF
(3) Typical figures are at T
J
= T
A
= 25°C and represent most likely parametric norm.
(4) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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