Datasheet

ADC12130, ADC12132, ADC12138
SNAS098G –MARCH 2000–REVISED MARCH 2013 www.ti.com
AC Electrical Characteristics (continued)
The following specifications apply for (V
+
= V
A
+ = V
D
+ = +5V, V
REF
+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+
= V
A
+ = V
D
+ = +3.3V, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), V
REF
− = 0V, 12-bit + sign conversion mode
(1)
, source impedance for analog inputs, V
REF
− and V
REF
+ ≤ 25Ω,
f
CK
= f
SK
= 5 MHz, and 10 (t
CK
) acquisition time unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25°C.
(2)
Parameter Test Conditions Typical
(3)
Limits
(4)
Units (Limits)
6(t
CK
) 6(t
CK
) (min)
7(t
CK
) (max)
6 Cycles Programmed
1.2 μs (min)
1.4 μs (max)
10(t
CK
) 10(t
CK
) (min)
11(t
CK
) (max)
10 Cycles Programmed
2.0 μs (min)
2.2 μs (max)
t
A
Acquisition Time
(5)
18(t
CK
) 18(t
CK
) (min)
19(t
CK
) (max)
18 Cycles Programmed
3.6 μs (min)
3.8 μs (max)
34(t
CK
) 34(t
CK
) (min)
35(t
CK
) (max)
34 Cycles Programmed
6.8 μs (min)
7.0 μs (max)
4944(t
CK
) 4944(t
CK
) (max)
t
CAL
Self-Calibration Time
988.8 μs (max)
76(t
CK
) 76(t
CK
) (max)
t
AZ
Auto Zero Time
15.2 μs (max)
2(t
CK
) 2(t
CK
) (min)
3(t
CK
) (max)
Self-Calibration or Auto Zero
t
SYNC
Synchronization Time from DOR
0.40 μs (min)
0.60 μs (max)
DOR High Time when CS is Low 9(t
SK
) 9(t
SK
) (max)
t
DOR
Continuously for Read Data and Software
1.8 μs (max)
Power Up/Down
8(t
SK
) 8(t
SK
) (max)
t
CONV
CONV Valid Data Time
1.6 μs (max)
(5) If SCLK and CCLK are driven from the same clock source, then t
A
is 6, 10, 18 or 34 clock periods minimum and maximum.
AC Electrical Characteristics
The following specifications apply for (V
+
= V
A
+ = V
D
+ = +5V, V
REF
+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+
= V
A
+ = V
D
+ = +3.3V, V
REF
+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), V
REF
− = 0V, 12-bit + sign conversion mode
(1)
, source impedance for analog inputs, V
REF
− and V
REF
+ ≤ 25Ω,
f
CK
= f
SK
= 5 MHz, and 10 (t
CK
) acquisition time unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25°C.
(2)
(Continued)
(1) The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device.
Therefore, the output data from these modes are not an indication of the accuracy of a conversion result.
(2) Timing specifications are tested at the TTL logic levels, V
OL
= 0.4V for a falling edge and V
OL
= 2.4V for a rising edge. TRI-STATE
output voltage is forced to 1.4V.
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