Datasheet

ADC12048
www.ti.com SNAS105B –APRIL 2000–REVISED MARCH 2013
Part Number Output Voltage Temperature
Tolerance Coefficient
LM4041CI-Adj ±0.5% ±100ppm/°C
LM4040AI-4.1 ±0.1% ±100ppm/°C
LM4050 ±0.2% ±50ppm/°C
LM4121 ±0.1% ±50ppm/°C
LM9140BYZ-4.1 ±0.5% ±25ppm/°C
Circuit of Figure 48 Adjustable ±2ppm/°C
OUTPUT DIGITAL CODE VERSUS ANALOG INPUT VOLTAGE
The ADC12048's fully differential 12-bit + sign ADC generates a two's complement output that is found by using
the equation shown below:
(3)
Round off the result to the nearest integer value between −4096 and 4095.
INPUT CURRENT
At the start of the acquisition window (t
AcqSYNOUT
) a charging current (due to capacitive switching) flows through
the analog input pins (CH0–CH7, ADCIN+ and ADCIN−, and the COM). The peak value of this input current will
depend on the amplitude and frequency of the input voltage applied, the source impedance and the input switch
ON resistance. With the MUXOUT+ connected to the ADCIN+ and the MUXOUT− connected to the ADCIN− the
on resistance is typically 2800Ω. Bypassing the MUX and using just the ADCIN+ and ADCIN− inputs the on
resistance is typically 2500Ω.
For low impedance voltage sources (<1000Ω for 12 MHz operation), the input charging current will decay to a
value that will not introduce any conversion errors before the end of the default sample-and-hold (S/H)
acquisition time (9 clock cycles). For higher source impedances (>1000Ω for 12 MHz operation), the S/H
acquisition time should be increased to allow the charging current to settle within specified limits. In
asynchronous mode, the acquisition time may be increased to 15, 47 or 79 clock cycles. If different acquisition
times are needed, the synchronous mode can be used to fully control the acquisition time.
INPUT BYPASS CAPACITANCE
External capacitors (0.01 μF–0.1 μF) can be connected between the analog input pins (CH0–CH7) and the
analog ground to filter any noise caused by inconductive pickup associated with long leads.
POWER SUPPLY CONSIDERATIONS
Decoupling and bypassing the power supply on a high resolution ADC is an important design task. Noise spikes
on the V
A
+ (analog supply) or V
D
+ (digital supply) can cause conversion errors. The analog comparator used in
the ADC will respond to power supply noise and will make erroneous conversion decisions. The ADC is
especially sensitive to power supply spikes that occur during the auto-zero or linearity calibration cycles.
The ADC12048 is designed to operate from a single +5V power supply. The separate supply and ground pins for
the analog and digital portions of the circuit allow separate external bypassing. To minimize power supply noise
and ripple, adequate bypass capacitors should be placed directly between power supply pins and their
associated grounds. Both supply pins should be connected to the same supply source. In systems with separate
analog and digital supplies, the ADC should be powered from the analog supply. At least a 10 μF tantalum
electrolytic capacitor in parallel with a 0.1 μF monolithic ceramic capacitor is recommended for bypassing each
power supply. The key consideration for these capacitors is to have low series resistance and inductance. The
capacitors should be placed as close as physically possible to the supply and ground pins with the smaller
capacitor closer to the device. The capacitors also should have the shortest possible leads in order to minimize
series lead inductance. Surface mount chip capacitors are optimal in this respect and should be used when
possible.
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