Datasheet

ADC12048
www.ti.com SNAS105B –APRIL 2000–REVISED MARCH 2013
SELECTABLE ACQUISITION TIME
The ADC12048's internal sample/hold circuitry samples an input voltage by connecting the input to an internal
sampling capacitor (approximately 70 pF) through an effective resistance equal to the multiplexer “On” resistance
(300Ω max) plus the “On” resistance of the analog switch at the input to the sample/hold circuit (2500Ω typical)
and the effective output resistance of the source. For conversion results to be accurate, the period during which
the sampling capacitor is connected to the source (the “acquisition time”) must be long enough to charge the
capacitor to within a small fraction of an LSB of the input voltage. An acquisition time of 750 ns is sufficient when
the external source resistance is less than 1 kΩ and any active or reactive source circuitry settles to 12 bits in
less than 500 ns. When source resistance or source settling time increase beyond these limits, the acquisition
time must also be increased to preserve precision.
In asynchronous (SYNC-OUT) mode, the acquisition time is controlled by an internal counter. The minimum
acquisition period is 9 clock cycles, which corresponds to the nominal value of 750 ns when the clock frequency
is 12 MHz. Bits b
4
and b
5
of the Configuration Register are used to select the acquisition time from among four
possible values (9, 15, 47, or 79 clock cycles). Since acquisition time in the asynchronous mode is based on
counting clock cycles, it is also inversely proportional to clock frequency:
(1)
Note that the actual acquisition time will be longer than T
ACQ
because acquisition begins either when the
multiplexer channel is changed or when RDY goes low, if the multiplexer channel is not changed. After a read is
performed, RDY goes high, which starts the T
ACQ
counter (see Figure 13).
In synchronous (SYNC-IN) mode, bits b
4
and b
5
are ignored, and the acquisition time depends on the sync signal
applied at the SYNC pin. If a new MUX channel is selected at the start of the conversion, the acquisition period
begins on the active edge of the WR signal that latches in the new MUX channel. If no new MUX channel is
selected, the acquisition period begins on the falling edge of RDY, which occurs at the end of the previous
conversion (or at the end of an autozero or autocalibration procedure). The acquisition period ends when SYNC
goes high.
To estimate the acquisition time necessary for accurate conversions when the source resistance is greater than
1 kΩ, use the following expression:
where
• R
S
is the source resistance
• R
M
is the MUX “On” resistance
• R
S/H
is the sample/hold “On” resistance (2)
If the settling time of the source is greater than 500 ns, the acquisition time should be about 300 ns longer than
the settling time for a “well-behaved”, smooth settling characteristic.
FULL CALIBRATION CYCLE
A full calibration cycle compensates for the ADC's linearity and offset errors. The converter's DC specifications
are specified only after a full calibration has been performed. A full calibration cycle is initiated by writing a Ful-
Cal command to the ADC12048. During a full calibration, the offset error is measured eight times, averaged and
a correction coefficient is created. The offset correction coefficient is stored in an internal offset correction
register.
The overall Iinearity correction is achieved by correctng the internal DAC's capacitor mismatches. Each capacitor
is compared eight times against all remaining smaller value capacitors. The errors are averaged and correction
coefficients are created.
Once the converter has been calibrated, an arithmetic logic unit (ALU) uses the offset and linearity correction
coefficients to reduce the conversion offset and linearity errors to within specified limits.
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