Datasheet
ADC12048
SNAS105B –APRIL 2000–REVISED MARCH 2013
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REGISTER BIT DESCRIPTION
CONFIGURATION REGISTER (Write Only)
This is a 13-bit write-only register that is used to program the functionality of the ADC12048. All data written to
the ADC12048 will always go to this register only. The contents of this register cannot be read.
MSB LSB
b
12
b
11
b
10
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
BW COMMAND FIELD SYNC HB SE ACQ TIME MUX ADDRESS
Power on State: 0100Hex
b
3
–b
0
: The MUX ADDRESS bits configure the analog input MUX. They select which input channels of the MUX
will connect to the MUXOUT+ and MUXOUT− pins. (Refer to INPUT MULTIPLEXER for more details on the
MUX.) Power-up value is 0000.
Table 1. MUX Channel Assignment
b
3
b
2
b
1
b
0
MUXOUT+ MUXOUT−
0 0 0 0 CH0 CH1
0 0 0 1 CH1 CH0
0 0 1 0 CH2 CH3
0 0 1 1 CH3 CH2
0 1 0 0 CH4 CH5
0 1 0 1 CH5 CH4
0 1 1 0 CH6 CH7
0 1 1 1 CH7 CH6
1 0 0 0 CH0 COM
1 0 0 1 CH1 COM
1 0 1 0 CH2 COM
1 0 1 1 CH3 COM
1 1 0 0 CH4 COM
1 1 0 1 CH5 COM
1 1 1 0 CH6 COM
1 1 1 1 CH7 COM
b
5
–b
4
: The ACQ TIME bits select one of four possible acquistion times in SYNC-OUT mode. (Refer to
SELECTABLE ACQUISITION TIME.)
b
5
b
4
Clocks
0 0 9
0 1 15
1 0 47
1 1 79
b
6
: When the Single-Ended bit (SE bit) is set, conversion results will be limited to positive values only and any
negative conversion results will appear as a code of zero in the Data register. The SE bit is cleared at power-up.
b
7
: The High Byte bit (HB) is meaningful only in 8-bit mode (BW bit b
12
= “0”) and is a don't care condition in 13-
bit mode (BW bit b
12
= “1”). This bit is used to access the upper byte of the Configuration Register in 8-bit mode.
When this bit is set and bit b
12
= 0, the next byte written to the ADC12048 will program the upper byte of the
Configuration register. The HB bit will automatically be cleared when data is written to the upper byte of the
Configuration register, allowing the lower byte to be accessed with the next write. The HB bit is cleared at
power-up.
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