Datasheet

ADC12048
SNAS105B –APRIL 2000–REVISED MARCH 2013 www.ti.com
Digital Timing Characteristics
The following specifications apply to the ADC12048, 13-bit data bus width, V
A
+ = V
D
+ = 5V, f
CLK
= 12 MHz, t
f
= 3 ns and C
L
=
50 pF on data I/O lines
Symbol Units
Parameter Conditions Typical
(1)
Limits
(2)
(Limit)
t
TPR
Throughput Rate Sync-Out Mode (SYNC Bit =
“0”) 9 Clock Cycles of 222 kHz
Acquisition Time
t
CSWR
Falling Edge of CS to Falling Edge of WR 0 ns
t
WRCS
Active Edge of WR to Rising Edge of CS 0 ns
t
WR
WR Pulse Width 20 30 ns (min)
t
WRSETFalling
Write Setup Time WMODE = “1” 20 ns (min)
t
WRHOLDFalling
Write Hold Time WMODE = “1” 5 ns (min)
t
WRSETRising
Write Setup Time WMODE = “0” 20 ns (min)
t
WRHOLDRising
Write Hold Time WMODE = “0” 5 ns (min)
t
CSRD
Falling Edge of CS to Falling Edge of RD 0 ns
t
RDCS
Rising Edge of RD to Rising Edge of CS 0 ns
t
RDDATA
Falling Edge of RD to Valid Data 8-Bit Mode (BW Bit = “0”) 40 58 ns (max)
t
RDDATA
Falling Edge of RD to Valid Data 13-Bit Mode (BW Bit = “1”) 26 44 ns (max)
t
RDHOLD
Read Hold Time 23 32 ns (max)
t
RDRDY
Rising Edge of RD to Rising Edge of RDY 24 38 ns (max)
t
WRRDY
Active Edge of WR to Rising Edge of RDY WMODE = “1” 42 65 ns (max)
t
STNDBY
WMODE = “0”. Writing the
Active Edge of WR to Falling Edge of STDBY Standby Command into the 200 230 ns (max)
Configuration Register
t
STDONE
WMODE = “0”. Writing the
Active Edge of WR to Rising Edge of STDBY RESET Command into the 30 45 ns (max)
Configuration Register
t
STDRDY
WMODE = “0”. Writing the
Active Edge of WR to Falling Edge of RDY RESET Command into the 1.4 2.5 ms (max)
Configuration Register
t
SYNC
Minimum SYNC Pulse Width 5 10 ns (min)
(1) Typicals are at T
A
= 25°C and represent most likely parametric norm.
(2) Limits are ensured to AOQL (Average Outgoing Quality Level).
Digital Timing Diagrams
Figure 3.
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