Datasheet

ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
www.ti.com SNAS080K –JULY 1999–REVISED MARCH 2013
DC and Logic Electrical Characteristics (continued)
The following specifications apply for V
+
= V
A
+ = V
D
+ = +5.0 V
DC
, V
REF
+ = +4.096 V
DC
, V
REF
− = 0 V
DC
, 12-bit + sign
conversion mode, f
CK
= f
SK
= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
= f
SK
= 5 MHz for
the ADC12030, ADC12032, ADC12034 and ADC12038, R
S
= 25Ω, source impedance for V
REF
+ and V
REF
− ≤ 25Ω, fully-
differential input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Boldface
limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25°C.
(1)(2)(3)
Units
Parameter Test Conditions Typical
(4)
Limits
(5)
(Limits)
V
OUT(0)
Logical “0” Output Voltage V
+
= 4.5V, I
OUT
= 1.6 mA 0.4 V (max)
V
OUT
= 0V −0.1 −3.0 µA (max)
I
OUT
TRI-STATE Output Current
V
OUT
= 5V 0.1 3.0 µA (max)
+I
SC
Output Short Circuit Source Current V
OUT
= 0V 14 6.5 mA (min)
−I
SC
Output Short Circuit Sink Current V
OUT
= V
D
+ 16 8.0 mA (min)
POWER SUPPLY CHARACTERISTICS
Digital Supply Current Awake 1.6 2.5 mA (max)
ADC12030, ADC12032, ADC12034 and CS = HIGH, Powered Down, CCLK on 600 µA
ADC12038 CS = HIGH, Powered Down, CCLK off 20 µA
I
D
+
Digital Supply Current Awake 2.3 3.2 mA
ADC12H030, ADC12H032, ADC12H034 CS = HIGH, Powered Down, CCLK on 0.9 mA
and ADC12H038 CS = HIGH, Powered Down, CCLK off 20 µA
Awake 2.7 4.0 mA (max)
I
A
+ Positive Analog Supply Current CS = HIGH, Powered Down, CCLK on 10 µA
CS = HIGH, Powered Down, CCLK off 0.1 µA
Awake 70 µA
I
REF
Reference Input Current
CS = HIGH, Powered Down 0.1 µA
AC Electrical Characteristics
The following specifications apply for V
+
= V
A
+ = V
D
+ = +5.0 V
DC
, V
REF
+ = +4.096 V
DC
, V
REF
− = 0 V
DC
, 12-bit + sign
conversion mode, t
r
= t
f
= 3 ns, f
CK
= f
SK
= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
= f
SK
= 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
S
= 25Ω, source impedance for V
REF
+ and V
REF
− ≤
25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25°C.
(1)
Typical ADC12H030/2/4/8 ADC12030/2/4/8 Units
Parameter Test Conditions
(2)
Limits
(3)
Limits
(3)
(Limits)
f
CK
Conversion Clock (CCLK) 10 8 5 MHz (max)
Frequency 1 MHz (min)
Serial Data Clock SCLK Frequency 10 8 5 MHz (max)
f
SK
0 Hz (min)
40 40 % (min)
Conversion Clock Duty Cycle
60 60 % (max)
40 40 % (min)
Serial Data Clock Duty Cycle
60 60 % (max)
12-Bit + Sign or 12- 44(t
CK
) 44(t
CK
) (max)
44(t
CK
)
Bit 5.5 8.8 µs (max)
t
C
Conversion Time
21(t
CK
) 21(t
CK
) (max)
8-Bit + Sign or 8-Bit 21(t
CK
)
2.625 4.2 µs (max)
(1) Timing specifications are tested at the TTL logic levels, V
IL
= 0.4V for a falling edge and V
IH
= 2.4V for a rising edge. TRI-STATE output
voltage is forced to 1.4V.
(2) Typical figures are at T
J
= T
A
= 25°C and represent most likely parametric norm.
(3) Tested limits are specified to AOQL (Average Outgoing Quality Level).
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ADC12H038